Interaction Between Precisely Placed Dopants and Interface Roughness in Silicon Nanowire Transistors: Full 3-D NEGF Simulation Study

In this work, we report a theoretical study based on quantum transport simulations that show the impact of the surface roughness on the performance of ultimately scaled gate-all-around silicon nanowire transistors (SNWT) with precisely positioned dopants designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green's Function (NEGF) formalism is used. The individual dopants and the profile of the channel surface roughness act as localized scatters and, hence, the impact on the electron transport is directly correlated to the combined effect of position of the single dopants and surface roughness shape. As a result, a large variation in the IOFF and ION and modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices without surface roughness. The variations of the current-voltage characteristics are analyzed with reference to the behaviour of the transmission coefficients, electron potential and electron concentration along the length of the device. Our calculations provide guidance for a future development of the next generation components with sub-10 nm dimensions for the semiconductor industry

Impact of randomly distributed dopants on Ω-gate junctionless silicon nanowire transistors

This paper presents experimental and simulation analysis of an Ω-shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for the 1.8-V gate overdrive with an OFF-current set at 100 nA/μm. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current-voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ID-VGs characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ID-VGs characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs

Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels

Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with the required characteristics for a specific application, however, poses some challenges. For example, a major challenge is that, as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). Some sources of this parasitic leakage current include quantum mechanical tunnelling, short channel effects and statistical variability [2, 3]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistors circuits employed globally in microprocessors, sensors and memories

Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength

Capacitance fluctuations in bulk MOSFETs due to random discrete dopants

Accuracy of timing in circuits and systems using nanoscale transistors is crucial and is dependent, to first order, on the capacitances of the load transistors. It is accepted that variation in parameters will be intrinsic to such devices due to, among other factors, the discrete nature of the doping. It is likely that one such parameter exhibiting variation will be capacitance. Here we investigate, using 3-dimensional simulation, the fluctuation in gate and drain capacitance in a 30 nm MOSFET due to random discrete doping

Perturbative vs non-perturbative impurity scattering in a narrow Si nanowire GAA transistor: A NEGF study

In this paper we study the effect of impurity scattering on the performance of a Si gate-all-around nanowire transistors. The non-equilibrium Green function formalism is used in order to describe the carrier transport. Impurity scattering is introduced using two different formalisms, one that considers the impurity potential as a small perturbation by introducing self energies and the other in which the impurity potential is described exactly by included the impurity potential through the Poisson equation. The non-perturbative method does not use a fitting parameter but the perturbative one uses a phenomenological constant that can be calibrated to match the result of the non-perturbative method. We confirm Ohms-law-type behaviour by using the perturbative approach for larger channel length

Increase in the Random Dopant Induced Threshold Fluctuations and Lowering in Sub 100 nm MOSFETs Due to Quantum Effects: A 3-D Density-Gradient Simulation Study

In this paper we present a detailed simulation study of the influence of quantum mechanical effects in the inversion layer on random dopant induced threshold voltage fluctuations and lowering in sub 100 nm MOSFETs. The simulations have been performed using a 3-D implementation of the density gradient (DG) formalism incorporated in our established 3-D atomistic simulation approach. This results in a self-consistent 3-D quantum mechanical picture, which implies not only the vertical inversion layer quantisation but also the lateral confinement effects related to current filamentation in the 'valleys' of the random potential fluctuations. We have shown that the net result of including quantum mechanical effects, while considering statistical dopant fluctuations, is an increase in both threshold voltage fluctuations and lowering. At the same time, the random dopant induced threshold voltage lowering partially compensates for the quantum mechanical threshold voltage shift in aggressively scaled MOSFETs with ultrathin gate oxides