Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation

Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, which fails to hold below 0.3V because of its vanishing noise margins. This paper examines the minimum-energy operation point of 2T and 3T1D e-DRAM gain cells at the 32-nm technology node with different design points: up-sizing transistors, using high- V th transistors, read/write wordline assists; as well as operating conditions (i.e., temperature). First, the e-DRAM cells are evaluated without considering any process variations. Then, a full-factorial statistical analysis of e-DRAM cells is performed in the presence of threshold voltage variations and the effect of upsizing on mean MEP is reported. Finally, it is shown that the product of the read and write lengths provides a knob to tradeoff energy-efficiency for reliable MEP energy operation.Peer ReviewedPostprint (author's final draft

Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm

3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.Peer ReviewedPostprint (author's final draft

Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm

Best DCIS Paper Award 20123T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.Peer ReviewedAward-winningPreprin

Proactive reconfiguration, a methodology for extending SRAM lifetime

The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique and furthermore it takes into account the process variability impact on the memory components. Our results show between a 30% and a 45% of system lifetime increase over the existing proactive reconfiguration technique and 1.7X to ~10X improvement to non-proactive reconfiguration one

Lepton flavour violation, Yukawa unification and neutrino masses in supersymmetric unified models

We explore some phenomenological consequences of models based on supersymmetric extensions of the Standard Model. In particular, we focus on the Minimal Supersymmetric Standard Model supplemented by right-handed neutrinos in the context of the Pati-Salam SU(4) x SU(2)_L x SU(2)_R Grand Unified Theory. We start by analysing the possibility of using Lepton Flavour Violation as a probe of physics beyond the Standard Model. We show that the #mu# #-># e#gamma# and #tau# #-># #mu##gamma# decays impose important constraints to the soft supersymmetry breaking parameters of the Pati-Salam model that already allow the formulation of lower bounds for the masses of the lighter supersymmetric particles. Secondly, we investigate how third family Yukawa unification can be used to provide a window into the soft supersymmetry breaking Lagrangian. We show that, a successful top quark mass prediction requires that the supersymmetric corrections to the bottom quark mass are small which, in turn, imposes a distinct hierarchy between the soft breaking parameters. Finally, we explicitly construct a realistic model of quark, charged lepton and neutrino masses and mixing angles, based on the Pati-Salam. gauge group supplemented by an abelian flavour symmetry, that can explain the large atmospheric neutrino mixing angle, suggested by the Super-Kamiokande data, and account for the large mixing angle Mikheyev-Smirnov-Wolfenstein solution to the solar neutrino problem. (author)Available from British Library Document Supply Centre-DSC:DXN040592 / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

Proactive reconfiguration, a methodology for extending SRAM lifetime

The proactive reconfiguration is an emerging technique that enlarges the lifetime of memory systems with embedded SRAM cells. This work introduces a novel version that modifies and enhances the advantages of this technique and furthermore it takes into account the process variability impact on the memory components. Our results show between a 30% and a 45% of system lifetime increase over the existing proactive reconfiguration technique and 1.7X to ~10X improvement to non-proactive reconfiguration one.Postprint (published version

SRAM lifetime improvement by using adaptive proactive reconfiguration

Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design strategies at the Nanoscale circuit system level. In this paper we have introduced an adaptive proactive reconfiguration technique that considers the inherent process variability (variability-aware) and BTI aging, and effectively enlarges the SRAM lifetime.Peer Reviewe

Growth and characterisation of single CuInSe2 crystals

SIGLEAvailable from British Library Document Supply Centre- DSC:D83043 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

SRAM lifetime improvement by using adaptive proactive reconfiguration

Modern generations of CMOS technology nodes are facing critical causes of hardware reliability failures, which were not significant in the past. Such vulnerabilities make it essential to investigate new robust design strategies at the Nanoscale circuit system level. In this paper we have introduced an adaptive proactive reconfiguration technique that considers the inherent process variability (variability-aware) and BTI aging, and effectively enlarges the SRAM lifetime.Peer ReviewedPostprint (published version

Process variability-aware proactive reconfiguration techniques for mitigating aging effects in nano scale SRAM lifetime

Process variations and device aging have a significant impact on the reliability and performance of nano scale integrated circuits. Proactive reconfiguration is an emerging technique to extend the lifetime of embedded SRAM memories. This work introduces a novel version that modifies and enhances the advantages of this method by considering the process variability impact on the memory components. Our results show between 30% and 45% SRAM lifetime increases over the existing proactive reconfiguration technique and between 1.7X and ~10X improvement over the non-proactive reconfiguration.Peer ReviewedPostprint (published version