An Exploratory Framework for Intelligent Labelling of Fault Datasets

Software fault prediction (SFP) has become a pivotal aspect in realm of software quality. Nevertheless, discipline of software quality suffers the starvation of fault datasets. Most of the research endeavors are focused on type of dataset, its granularity, metrics used and metrics extractors. However, sporadic attention has been exerted on development of fault datasets and their associated challenges. There are very few publicly available datasets limiting the possibilities of comprehensive experiments on way to improvising the quality of software. Current research targets to address the challenges pertinent to fault dataset collection and development if one is not available publicly. It also considers dynamic identification of available resources such as public dataset, open-source software archieves, metrics parsers and intelligent labeling techniques. A framework for dataset collection and development process has been furnished along with evaluation procedure for the identified resources

Modeling and control of a voltage-lift cell split-source inverter with MPPT for photovoltaic systems

In this study, a new single-stage inverter with improved boosting performance was proposed to enhance the recently developed split-source inverter (SSI) topology. The study introduced new SSI configurations with high voltage gain. The proposed design features a voltage-lift cell made of capacitors, inductors, and diodes, which increases the boosting capability. The decoupled control technique, where The DC input current is controlled by the AC modulation signals,allows for independent adjustment of both the DC input and AC output current. The research also employed a modified space vector modulation approach to manage the inverter switches and reduce current ripple. The combination of the proposed topology and the modified SVPWM scheme significantly improves the DC-boosting capabilities. the validity of the proposed solution was confirmed through simulation using three-phase SSI models in MATLAB/SIMULINK®. Finally, The validity of the simulation and experimental investigation of the analysis and performance of the topologies provided

Robust H∞ output feedback control of bidirectional inductive power transfer systems

Bidirectional Inductive power transfer (IPT) systems behave as high order resonant networks and hence are highly sensitive to changes in system parameters. Traditional PID controllers often fail to maintain satisfactory power regulation in the presence of parametric uncertainties. To overcome these problems, this paper proposes a robust controller which is designed using linear matrix inequality (LMI) techniques. The output sensitivity to parametric uncertainty is explored and a linear fractional transformation of the nominal model and its uncertainty is discussed to generate a standard configuration for μ-synthesis and LMI analysis. An H∞ controller is designed based on the structured singular value and LMI feasibility analysis with regard to uncertainties in the primary tuning capacitance, the primary and pickup inductors and the mutual inductance. Robust stability and robust performance of the system is studied through μ-synthesis and LMI feasibility analysis. Simulations and experiments are conducted to verify the power regulation performance of the proposed controller

Design and implementation of a new unity gain nine-level active neutral point clamped multilevel inverter topology

The major issue with the three-level active neutral point clamped (ANPC) inverter has been the requirement of a higher DC-link voltage with a lower peak of the output voltage. In this study, a new unity gain ANPC multilevel inverter topology has been proposed with a lower number of switches. The proposed topology generates a nine-level output voltage with a single DC voltage source, four capacitors, and ten switches. The two floating capacitors have a voltage rating of 0.25Vdc which reduces the overall cost and improves the efficiency of the topology. The performance of the proposed topology has been demonstrated using various comparisons and experimental results.This publication was made possible by Qatar University-Marubeni Concept to Prototype Development Research grant # [M-CTP-CENG-2020-2] from the Qatar University. The statements made herein are solely the responsibility of the authors.Scopu

Optimal Allocation of Multiple Distributed Generators and Shunt Capacitors in Distribution System Using Flower Pollination Algorithm

Optimal siting and sizing of Distributed generators (DGs) and capacitors helps in enhancing the overall performance of distribution system. A proficient method to optimally allocate DGs and shunt capacitors in distribution system is proposed in this paper. The major objectives of the work are power loss reduction, voltage profile improvement and operating cost minimization. A standard IEEE 33 bus test system with constant power load at various load levels is considered for the analysis. Optimal siting of DGs and capacitors is carried out using sensitivity analysis technique. Further Flower pollination algorithm is employed for optimal sizing of DGs and capacitors and the results are compared with few other noteworthy methods.Scopu

A multilevel inverter topology using diode half-bridge circuit with reduced power component

This paper presents a new multilevel converter with a reduced number of power components for medium voltage applications. Both symmetric and asymmetric structures of the presented multilevel converter are proposed. The symmetric topology requires equal dc source values, whereas the asymmetric topology uses minimum switch count. However, both structures suffer from high blocking voltage across the switches. To reduce the blocking voltage on switches, an optimal topology is presented and analyzed for the selection of the minimum number of switches and dc sources, while maintaining a low blocking voltage across the switches. A comparative analysis with recently published topologies was performed. The simulation results, as well as the comparative analysis, validated the robustness and effectiveness of the proposed topology in terms of the reduced power loss, lowered number of components, and cost. Furthermore, in addition to the simulation results, the performance of the proposed topology was verified using experimental results of 9, 17, and 25 evels.