Author retrospective for the dual data cache

In this paper we present a retrospective on our paper published in ICS 1995, which to best of our knowledge was the first paper that introduced the concept of a cache memory with multiple subcaches, each tuned for a different type of locality. In this retrospective, we summarize the main ideas of the original paper and outline some of the later work that exploited similar ideas and could have been influenced by our original paper, including two actual industrial microprocessors.Peer ReviewedPostprint (author’s final draft

Predicting topology propagation messages in mobile ad hoc networks: The value of history

This research was funded by the Spanish Government under contracts TIN2016-77836-C2-1-R,TIN2016-77836-C2-2-R, and DPI2016-77415-R, and by the Generalitat de Catalunya as Consolidated ResearchGroups 2017-SGR-688 and 2017-SGR-990.The mobile ad hoc communication in highly dynamic scenarios, like urban evacuations or search-and-rescue processes, plays a key role in coordinating the activities performed by the participants. Particularly, counting on message routing enhances the communication capability among these actors. Given the high dynamism of these networks and their low bandwidth, having mechanisms to predict the network topology offers several potential advantages; e.g., to reduce the number of topology propagation messages delivered through the network, the consumption of resources in the nodes and the amount of redundant retransmissions. Most strategies reported in the literature to perform these predictions are limited to support high mobility, consume a large amount of resources or require training. In order to contribute towards addressing that challenge, this paper presents a history-based predictor (HBP), which is a prediction strategy based on the assumption that some topological changes in these networks have happened before in the past, therefore, the predictor can take advantage of these patterns following a simple and low-cost approach. The article extends a previous proposal of the authors and evaluates its impact in highly mobile scenarios through the implementation of a real predictor for the optimized link state routing (OLSR) protocol. The use of this predictor, named OLSR-HBP, shows a reduction of 40–55% of topology propagation messages compared to the regular OLSR protocol. Moreover, the use of this predictor has a low cost in terms of CPU and memory consumption, and it can also be used with other routing protocols.Peer ReviewedPostprint (published version

Minimulticomputador de bajo coste

En la mayoría de los estudios de Grado en Ingeniería Informática hay asignaturas que abordan el tema de la supercomputación. Uno de sus objetivos es adquirir competencias en programación paralela. Para realizar ejercicios y prácticas se suelen usar estándares como OpenMP, MPI y CUDA. Para programar con dichos estándares se usan sistemas de elevado precio, lo que hace que el presupuesto disponible limite el número de procesadores. Por lo tanto, el acceso a un supercomputador con cientos de procesadores (que supone centenares de miles de euros) no parece estar justificado para realizar prácticas con los estudiantes. Sin embargo, y siguiendo la tendencia de usar muchos procesadores pero poco potentes basados en ARM, se puede construir un minimulticomputador de bajo coste por un precio equivalente a un servidor de memoria compartida. Este trabajo presenta un recurso docente basado en placas de HardKernel, que integran 64 placas Odroid y que mediante Gigabit-Ethernet permiten montar un servidor de programación MPI con 256 procesadores. Si bien se trata de un recurso de bajas prestaciones, es interesante el hecho de tener acceso a centenares de procesadores para poder hacer estudios de escalabilidad, manteniendo un buen compromiso entre prestaciones, precio y consumo.In most of Computer Science Degrees, there are subjects that address the topic of supercomputing. One of the objectives of these subjects is to acquire competences in parallel programming. To carry out exercises and practices, standards such as OpenMP, MPI and CUDA are often used. Unfortunately, the most suitable systems to deal with those standards are very expensive and most of the times the available budget limits the number of processors. Owning a supercomputer with hundreds of processors (that means hundreds of thousands of euros) does not seem to be justified in a teaching environment. However, assuming the trend of dealing with many low-power processors (based on ARM architectures), a low-cost minimulticomputer can be built for a price equivalent to a shared memory server. In this work, we present a teaching resource based on HardKernel boards, with 64 Odroid boards connected through Gigabit-Ethernet, to build a MPI server with 256 processors. Although it is a resource with a relatively low performance, the aim is to have access to hundreds of processors to be able to carry out scalability analysis and, above all, maintaining a good trade-off between performance, price and energy consumption.Este trabajo ha contado con la financiación del Gobierno de España bajo los contratos TIN2016-77836-C2-1-R, TIN2016-77836-C2-2-R, TIN2016-75344-R y DPI2016-77415-R, y también de la Generalitat de Catalunya como Grupos de Investigación Consolidados 2017-SGR-688 y 2017-SGR-990

Predicting topology propagation messages in mobile ad hoc networks: The value of history

The mobile ad hoc communication in highly dynamic scenarios, like urban evacuations or search-and-rescue processes, plays a key role in coordinating the activities performed by the participants. Particularly, counting on message routing enhances the communication capability among these actors. Given the high dynamism of these networks and their low bandwidth, having mechanisms to predict the network topology offers several potential advantages; e.g., to reduce the number of topology propagation messages delivered through the network, the consumption of resources in the nodes and the amount of redundant retransmissions. Most strategies reported in the literature to perform these predictions are limited to support high mobility, consume a large amount of resources or require training. In order to contribute towards addressing that challenge, this paper presents a history-based predictor (HBP), which is a prediction strategy based on the assumption that some topological changes in these networks have happened before in the past, therefore, the predictor can take advantage of these patterns following a simple and low-cost approach. The article extends a previous proposal of the authors and evaluates its impact in highly mobile scenarios through the implementation of a real predictor for the optimized link state routing (OLSR) protocol. The use of this predictor, named OLSR-HBP, shows a reduction of 40–55% of topology propagation messages compared to the regular OLSR protocol. Moreover, the use of this predictor has a low cost in terms of CPU and memory consumption, and it can also be used with other routing protocols.Fil: Millán, Pere. Universitat Rovira I Virgili; EspañaFil: Aliagas, Carles. Universitat Rovira I Virgili; EspañaFil: Molina, Carlos. Universitat Rovira I Virgili; EspañaFil: Meseguer, Roc. Universidad Politécnica de Catalunya; EspañaFil: Ochoa, Sergio F.. Universidad de Chile; ChileFil: Santos, Rodrigo Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Ciencias e Ingeniería de la Computación. Universidad Nacional del Sur. Departamento de Ciencias e Ingeniería de la Computación. Instituto de Ciencias e Ingeniería de la Computación; Argentina. Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras; Argentin

A low-cost and do-it-yourself device for pumping monitoring in deep aquifers

Water crises due to climate change, high population growth and increasing demands from industry and agriculture claim for increasing efficiency and universalizing water resources management strategies and techniques. Water monitoring helps providing necessary evidences for making sound decisions about managing water resources both now and in the future. In this work, a low cost and “do it yourself” communication device is proposed to record water production and energy consumption of electric pumpings from deep boreholes/wells, and to predict the impact of the ongoing and previous pumpings in the evolution of the water level in the aquifer. The proposal incorporates an edge-computing approach for the simulation of the aquifer response in real-time. Computation of results of interest is performed at the sensor, minimizing communication requirements and ensuring almost immediate results. An approximated solution to physically based modeling of aquifer response is computed thanks to the a priori expression of the water level time evolution in a reduced basis. The accuracy is enough to detect deviations from expected behaviour. The energy consumption of the device is very much reduced with respect to that of a full modelling, which can be computed off-line for calibrating reduced model parameters and perform detailed analyses. The device is tested in a real scenario, in a mountain subbasin of the Ebro river in Spain, obtaining a good trade-off between performance, price, and energy consumption.This research has been partly supported by EU under grant agreement N. 825184 and funded by the Government of Spain under contracts PID2019-106774RB-C21, PID2019-106774RB-C22, and PID2020-113172RB-I00 and by the Government of Catalonia as Consolidated Research Groups 2017-SGR-688 and 2017-SGR-990, and Pre-consolidated Research Group 2017-SGR-1496. The APC was funded by the Open program from Universitat Rovira i Virgili.Peer ReviewedPostprint (published version

Minimulticomputador de bajo coste

En la mayoría de los estudios de Grado en Ingeniería Informática hay asignaturas que abordan el tema de la supercomputación. Uno de sus objetivos es adquirir competencias en programación paralela. Para realizar ejercicios y prácticas se suelen usar estándares como OpenMP, MPI y CUDA. Para programar con dichos estándares se usan sistemas de elevado precio, lo que hace que el presupuesto disponible limite el número de procesadores. Por lo tanto, el acceso a un supercomputador con cientos de procesadores (que supone centenares de miles de euros) no parece estar justificado para realizar prácticas con los estudiantes. Sin embargo, y siguiendo la tendencia de usar muchos procesadores pero poco potentes basados en ARM, se puede construir un minimulticomputador de bajo coste por un precio equivalente a un servidor de memoria compartida. Este trabajo presenta un recurso docente basado en placas de HardKernel, que integran 64 placas Odroid y que mediante Gigabit-Ethernet permiten montar un servidor de programación MPI con 256 procesadores. Si bien se trata de un recurso de bajas prestaciones, es interesante el hecho de tener acceso a centenares de procesadores para poder hacer estudios de escalabilidad, manteniendo un buen compromiso entre prestaciones, precio y consumo.Este trabajo ha contado con la financiación del Gobierno de España bajo los contratos TIN2016-77836-C2-1-R, TIN2016-77836-C2-2-R, TIN2016-75344-R y DPI2016-77415-R, y también de la Generalitat de Catalunya como Grupos de Investigación Consolidados 2017-SGR-688 y 2017-SGR-990Peer ReviewedPostprint (published version

Author retrospective for the dual data cache

In this paper we present a retrospective on our paper published in ICS 1995, which to best of our knowledge was the first paper that introduced the concept of a cache memory with multiple subcaches, each tuned for a different type of locality. In this retrospective, we summarize the main ideas of the original paper and outline some of the later work that exploited similar ideas and could have been influenced by our original paper, including two actual industrial microprocessors.Peer Reviewe

Author retrospective for the dual data cache

In this paper we present a retrospective on our paper published in ICS 1995, which to best of our knowledge was the first paper that introduced the concept of a cache memory with multiple subcaches, each tuned for a different type of locality. In this retrospective, we summarize the main ideas of the original paper and outline some of the later work that exploited similar ideas and could have been influenced by our original paper, including two actual industrial microprocessors.Peer Reviewe

Time Series Analysis to Predict End-to-End Quality of Wireless Community Networks

Community Networks have been around us for decades being initially deployed in the USA and Europe. They were designed by individuals to provide open and free “do it yourself” Internet access to other individuals in the same community and geographic area. In recent years, they have evolved as a viable solution to provide Internet access in developing countries and rural areas. Their social impact is measurable, as the community is provided with the right and opportunity of communication. Community networks combine wired and wireless links, and the nature of the wireless medium is unreliable. This poses several challenges to the routing protocol. For instance, Link-State routing protocols deal with End-to-End Quality tracking to select paths that maximize the delivery rate and minimize traffic congestion. In this work, we focused on End-to-End Quality prediction by means of time-series analysis to foresee which paths are more likely to change their quality. We show that it is possible to accurately predict End-to-End Quality with a small Mean Absolute Error in the routing layer of large-scale, distributed, and decentralized networks. In particular, we analyzed the path ETX behavior and properties to better identify the best prediction algorithm. We also analyzed the End-to-End Quality prediction accuracy some steps ahead in the future, as well as its dependency on the hour of the day. Besides, we quantified the computational cost of the prediction. Finally, we evaluated the impact of the usage for routing of our approach versus a simplified OLSR (ETX + Dijkstra) on an overloaded network

A low-cost multicomputer for teaching environments

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksWe propose a teaching resource that uses Hard Kernel boards to build an MPI server with 256 cores. Although this system has a relatively low performance, the aim is to provide access to hundreds of cores for carrying out scalability analyses, while obtaining a good trade-off between performance, price, and energy consumption. Here, we give details about the implementation of this system at both the hardware and software levels. We also explain how it was used to teach parallel programming in a university degree course, and discuss the teachers’ and students’ comments about using this new system.This work has been funded by the Government of Spain undercontractsTIN2016-77836-C2-1-R, TIN2016-77836-C2-2-R,TIN2016-75344-R and DPI2016-77415-R, and by the Governmentof Catalonia as Consolidated Research Groups 2017-SGR-688 and 2017-SGR-990Peer ReviewedPostprint (published version