TV series and movies in the teaching of legal english vocabulary

76 Páginas.This project was the result of searching for a meaningful way in which to teach Legal English. This research study examines how movies and TV series can be used for this purpose. This project was conducted at Universidad Santo Tomás, Bogotá branch, with a group of 22 students studying their ninth semester of Law with an Upper Intermediate level of proficiency. In previous courses, these students had to learn legal concepts in their L1 (Spanish) and this course was their first one dealing with legal concepts in their L2 (English). TV series such as The Simpsons and Shark were used for this purpose as well as extracts from movies namely Liar Liar and The Green Mile. In order to take advantage of these types of videos, several workshops were designed. A Qualitative Action Research Study was used to conduct this project. In order to collect data diaries and surveys were used and video transcripts were taken from the students’ trials. The findings of this project suggest the manner in which students learned and were also able to enjoy this experience. The researcher found a meaningful way to teach legal vocabulary. Furthermore, it was demonstrated that the participants did not only learn legal vocabulary but also legal content. Thus, when movies and TV series are well exploited, they become an excellent aid for the language class

CellSim: a validated modular heterogeneous multiprocessor simulator

As the number of transistors on a chip continues increasing the power consumption has become the most important constraint in processors design. Therefore, to increase performance, computer architects have decided to use multiprocessors. Moreover, recent studies have shown that heterogeneous chip multiprocessors have greater potential than homogeneous ones. We have built a modular simulator for heterogeneous multiprocessors that can be configure to model IBM's Cell Processor. The simulator has been validated against the real machine to be used as a research tool.Peer ReviewedPostprint (published version

TaskPoint: sampled simulation of task-based programs

Sampled simulation is a mature technique for reducing simulation time of single-threaded programs, but it is not directly applicable to simulation of multi-threaded architectures. Recent multi-threaded sampling techniques assume that the workload assigned to each thread does not change across multiple executions of a program. This assumption does not hold for dynamically scheduled task-based programming models. Task-based programming models allow the programmer to specify program segments as tasks which are instantiated many times and scheduled dynamically to available threads. Due to system noise and variation in scheduling decisions, two consecutive executions on the same machine typically result in different instruction streams processed by each thread. In this paper, we propose TaskPoint, a sampled simulation technique for dynamically scheduled task-based programs. We leverage task instances as sampling units and simulate only a fraction of all task instances in detail. Between detailed simulation intervals we employ a novel fast-forward mechanism for dynamically scheduled programs. We evaluate the proposed technique on a set of 19 task-based parallel benchmarks and two different architectures. Compared to detailed simulation, TaskPoint accelerates architectural simulation with 64 simulated threads by an average factor of 19.1 at an average error of 1.8% and a maximum error of 15.0%.This work has been supported by the Spanish Government (Severo Ochoa grants SEV2015-0493, SEV-2011-00067), the Spanish Ministry of Science and Innovation (contract TIN2015-65316-P), Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), the RoMoL ERC Advanced Grant (GA 321253), the European HiPEAC Network of Excellence and the Mont-Blanc project (EU-FP7-610402 and EU-H2020-671697). M. Moreto has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship JCI-2012-15047. M. Casas is supported by the Ministry of Economy and Knowledge of the Government of Catalonia and the Cofund programme of the Marie Curie Actions of the EUFP7 (contract 2013BP B 00243). T.Grass has been partially supported by the AGAUR of the Generalitat de Catalunya (grant 2013FI B 0058).Peer ReviewedPostprint (author's final draft

Chambers of comerce: correspondence of its institutional function towards the impact and growth of the business sector

El presente estudio plantea la necesidad de analizar a las cámaras empresariales desde el enfoque de la teoría de las instituciones. El objetivo principal de esta investigación es determinar, como un primer intento, la correspondencia que existe entre el cumplimiento de la función institucional de las cámaras empresariales y el impacto que genera en el desarrollo del sector empresarial en el municipio de Querétaro con la actitud reflexiva de los empresarios. La presente investigación es un estudio exploratorio que utiliza una metodología de carácter cualitativo basado en la fenomenología. La muestra se definió de acuerdo con un muestreo no probabilístico de juicio secuencial, hasta determinar una saturación de categoría. Se utilizó como herramienta de recolección de información una guía de entrevista semiestructurada; el contacto que se obtuvo con los integrantes del sector empresarial fue con los propietarios de empresas micro y pequeñas de los sectores secundario y terciario con afiliación a alguna cámara empresarial.The present study raised from the need to analize the different chambers of commerce from the perspective of the institutional theory. The principal objective of this research is to determine, in a first attempt, the correspondence that exists between the compliance of the institutional function of the chambers of commerce and the impact generated on the growth in the business sector in the Queretaro municipality, through the reflection of the businessmen. The present investigation is classified as an exploratory study. For this condition it is precise to use a methology of qualitative character through phenomenology. To be able to define the effects the sample group it establishes the use of a not probabilistic model of sequencial judgement until a categorical saturation can be dertermined. A semistructural interview has been used as a recolection tool of information; members that have been contacted in business sector has been with the owners or general managers of micro and small businesses of the second and third sectors

Coinfection of Hepatitis B and C in HIV Patients: A Review of the State of the Art

Infection with the human immunodeficiency virus (HIV) modifies the course of infection by the virus of hepatitis B (HBV) by several mechanisms: the rate of chronicity, prolonging viremia by HBV, and increase in morbidity related to liver disease. The treatment for both infections should be done in a coordinated manner, to avoid the emergence of resistance in HIV, HBV or both, as well as major alterations in the hepatic enzymes. Monotherapies with lamivudine or emtricitabine select, rapidly, mutant strains of the HBV and HIV. Monotherapy with adefovir has moderate effects in coinfected patients as they already have mutations. If the treatment of HBV can defer until the combination antiretroviral therapy of HIV is necessary, these patients should receive a combination of tenofovir plus lamivudine (or emtricitabine), since this provides a powerful therapy against HBV and establishes a good central axis for antiretroviral therapy. In addition, it would prevent the selection of HBV variant resistance. The influence of HIV in the HCV infection. Increase in load HIV-driven viral hepatitis exacerbates hepatic lesions and influences transmission of the HCV. The risk of sexual transmission increases when HIV is present in the carrier. Coinfection modifies the evolution of fibrosis in patients with HIV, with higher speed in those who have low CD4 counts, so that the onset of cirrhosis occurs before, and the risk of liver decompensation is also more frequent. The consequence of this situation is an increase in liver-related morbidity and mortality

Rebalancing the core front-end through HPC code analysis

There is a need to increase performance under the same power and area envelope to achieve Exascale technology in high performance computing (HPC). The today's chip multiprocessor (CMP) design is tailored by traditional desktop and server workloads, different from parallel applications commonly run in HPC. In this work, we focus on the HPC code characteristics and processor front-end which factors around 30% of core power and area on the emerging lean-core type of processors used in HPC. Separating serial from parallel code sections inside applications, we characterize three HPC benchmark suites and compare them to a traditional set of desktop integer workloads. HPC applications have biased and mostly backward taken branches, small dynamic instruction footprints, and long basic blocks. Our findings suggest smaller branch predictors (BP) with the additional loop BP, smaller branch target buffers (BTB), and smaller L1 instruction caches (I-cache) with wider lines. Still, the aforementioned downsizing applies only to the cores meant to run parallel code. The difference between serial and parallel code sections in HPC applications points to an asymmetric CMP design, with one baseline core for sequential and many HPCtailored cores designed for parallel code. Predictions using Sniper simulator and McPAT show that an HPC-tailored lean core saves 16% of the core area and 7% of power compared to a baseline core, without performance loss. Using the area savings to add an extra core, an asymmetric CMP with one baseline and eight tailored cores has the same area budget as a symmetric CMP composed out of eight baseline cores demanding 4% more power and providing 12% shorter execution time on average.Postprint (author's final draft

Adaptive runtime-assisted block prefetching on chip-multiprocessors

Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution.Peer ReviewedPostprint (author's final draft