Analyzing capacitance-voltage measurements of vertical wrapped-gated nanowires

The capacitance of arrays of vertical wrapped-gate InAs nanowires are analyzed. With the help of a Poisson-Schr"odinger solver, information about the doping density can be obtained directly. Further features in the measured capacitance-voltage characteristics can be attributed to the presence of surface states as well as the coexistence of electrons and holes in the wire. For both scenarios, quantitative estimates are provided. It is furthermore shown that the difference between the actual capacitance and the geometrical limit is quite large, and depends strongly on the nanowire material.Comment: 15 pages, 6 Figures included, to appear in Nanotechnolog

Unipolar and bipolar operation of InAs/InSb nanowire heterostructure field-effect transistors

We present temperature dependent electrical measurements on n-type InAs/InSb nanowireheterostructurefield-effect transistors. The barrier height of the heterostructure junction is determined to be 220 meV, indicating a broken bandgap alignment. A clear asymmetry is observed when applying a bias to either the InAs or the InSb side of the junction. Impact ionization and band-to-band tunneling is more pronounced when the large voltage drop occurs in the narrow bandgapInSb segment. For small negative gate-voltages, the InSb segment can be tuned toward p-type conduction, which induces a strong band-to-band tunneling across the heterostructucture junction.This work was carried out within the Nanometer Structure Consortium at Lund University and was supported by the Swedish Research Council (VR), the Swedish Foundation for Strategic Research (SSF), and the Knut and Alice Wallenberg Foundation

Correlation-induced conductance suppression at level degeneracy in a quantum dot

The large, level-dependent g-factors in an InSb nanowire quantum dot allow for the occurrence of a variety of level crossings in the dot. While we observe the standard conductance enhancement in the Coulomb blockade region for aligned levels with different spins due to the Kondo effect, a vanishing of the conductance is found at the alignment of levels with equal spins. This conductance suppression appears as a canyon cutting through the web of direct tunneling lines and an enclosed Coulomb blockade region. In the center of the Coulomb blockade region, we observe the predicted correlation-induced resonance, which now turns out to be part of a larger scenario. Our findings are supported by numerical and analytical calculations.Comment: 5 pages, 4 figure

Temperature dependent properties of InSb and InAs nanowire field-effect transistors

We present temperature dependent electrical measurements on InSb and InAs nanowire field-effect transistors (FETs). The FETs are fabricated from InAs/InSb heterostructure nanowires, where one complete transistor is defined within each of the two segments. Both the InSb and the InAs FETs are n-type with good current saturation and low voltage operation. The off-current for the InSb FET shows a strong temperature dependence, which we attribute to a barrier lowering due to an increased band-to-band tunneling in the drain part of the channel.This work was carried out within the Nanometer Structure Consortium at Lund University and was supported by the Swedish Research Council VR, the Swedish Foundation for Strategic Research SSF, the European Community EU Contract No. 015783 NODE, and the Knut and Alice Wallenberg Foundation

High-k/InGaAs interface defects at cryogenic temperature

Oxide defects in the high-k/InGaAs MOS system are investigated. The behaviour of these traps is explored from room temperature down to 10 K. This study reveals that the exchange of free carriers between oxide states and either the conduction or the valence band is strongly temperature dependant. The capture and emission of electrons is strongly suppressed at 10 K as demonstrated by the collapse of the capacitance frequency dispersion in accumulation for n-InGaAs MOS devices, though hysteresis in the C-V sweeps is still present at 10 K. Phonon assisted tunnelling processes are considered in the simulation of electrical characteristics. The simulated data match very well the experimental characteristics and provide energy and spatial mapping of oxide defects. The multi phonon theory also help explain the impedance data temperature dependence. This study also reveals an asymmetry in the free carrier trapping between n and p type devices, where hole trapping is more significant at 10 K

Response of young and adult birds to the same environmental variables and different spatial scales during post breeding period

Context: How do young birds achieve spatial knowledge about the environment during the initial stages of their life? They may follow adults, so gaining social information and learning; alternatively, young birds may acquire knowledge of the environment themselves by experiencing habitat and landscape features. If learning is at least partially independent of adults then young birds should respond to landscape composition at finer spatial scale than adults, who possess knowledge over a larger area. Objectives: We studied the responses of juvenile, immature and adult Caspian Gull Larus cachinnans to the same habitat and landscape variables, but at several spatial scales (ranging from 2.5 to 15\ua0km), during post-breeding period. Methods: We surveyed 61 fish ponds (foraging patches) in southern Poland and counted Caspian gulls. Results: Juvenile birds responded at finer spatial scales to the factors than did adults. Immature birds showed complicated, intermediate responses to spatial scale. The abundance of juvenile birds was mostly correlated with the landscape composition (positively with the cover of corridors and negatively with barriers). Adult abundance was positively related to foraging patch quality (fish stock), which clearly required previous spatial experience of the environment. The abundance of all age classes were moderately correlated with each other indicating that social behaviour may also contribute to the learning of the environment. Conclusions: This study shows that as birds mature, they respond differently to components of their environment at different spatial scales. This has considerable ecological consequences for their distribution across environments

Neuroplasticity pathways and protein-interaction networks are modulated by vortioxetine in rodents

Additional file 2: Figure S1. Merged mouse and rat network (mapped to human proteins) and summary of biological functions of each sub-network. Biological functions were manually extracted from the Function and Gene Ontology fields of the UniProt protein entries. The genes with dark, bold borders were used to build the network of protein–protein interaction partners. Squares with bold borders represent upregulated targets from the rat network, and circles with bold borders indicate differentially-regulated targets from the mouse network. The arrowheads indicate the common targets found in mouse and rat networks. This network of physically-interacting proteins containing clusters related to synaptic plasticity, synaptic transmission, neurodevelopment, cell growth, metabolism, and apoptosis, was significantly modulated in both mouse and rat

III-V compound semiconductor transistors—from planar to nanowire structures

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III-V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III-V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS application