Cellular responses of Candida albicans to phagocytosis and the extracellular activities of neutrophils are critical to counteract carbohydrate starvation, oxidative and nitrosative stress

Acknowledgments We thank Alexander Johnson (yhb1D/D), Karl Kuchler (sodD/D mutants), Janet Quinn (hog1D/D, hog1/cap1D/D, trx1D/D) and Peter Staib (ssu1D/D) for providing mutant strains. We acknowledge helpful discussions with our colleagues from the Microbial Pathogenicity Mechanisms Department, Fungal Septomics and the Microbial Biochemistry and Physiology Research Group at the Hans Kno¨ll Institute (HKI), specially Ilse D. Jacobsen, Duncan Wilson, Sascha Brunke, Lydia Kasper, Franziska Gerwien, Sea´na Duggan, Katrin Haupt, Kerstin Hu¨nniger, and Matthias Brock, as well as from our partners in the FINSysB Network. Author Contributions Conceived and designed the experiments: PM HW IMB AJPB OK BH. Performed the experiments: PM CD HW. Analyzed the data: PM HW IMB AJPB OK BH. Wrote the paper: PM HW OK AJPB BH.Peer reviewedPublisher PD

Increased chromosomal radiosensitivity in asymptomatic carriers of a heterozygous BRCA1 mutation

Background: Breast cancer risk increases drastically in individuals carrying a germline BRCA1 mutation. The exposure to ionizing radiation for diagnostic or therapeutic purposes of BRCA1 mutation carriers is counterintuitive, since BRCA1 is active in the DNA damage response pathway. The aim of this study was to investigate whether healthy BRCA1 mutations carriers demonstrate an increased radiosensitivity compared with healthy individuals. Methods: We defined a novel radiosensitivity indicator (RIND) based on two endpoints measured by the G2 micronucleus assay, reflecting defects in DNA repair and G2 arrest capacity after exposure to doses of 2 or 4 Gy. We investigated if a correlation between the RIND score and nonsense-mediated decay (NMD) could be established. Results: We found significantly increased radiosensitivity in the cohort of healthy BRCA1 mutation carriers compared with healthy controls. In addition, our analysis showed a significantly different distribution over the RIND scores (p = 0.034, Fisher’s exact test) for healthy BRCA1 mutation carriers compared with non-carriers: 72 % of mutation carriers showed a radiosensitive phenotype (RIND score 1–4), whereas 72 % of the healthy volunteers showed no radiosensitivity (RIND score 0). Furthermore, 28 % of BRCA1 mutation carriers had a RIND score of 3 or 4 (not observed in control subjects). The radiosensitive phenotype was similar for relatives within several families, but not for unrelated individuals carrying the same mutation. The median RIND score was higher in patients with a mutation leading to a premature termination codon (PTC) located in the central part of the gene than in patients with a germline mutation in the 5′ end of the gene. Conclusions: We show that BRCA1 mutations are associated with a radiosensitive phenotype related to a compromised DNA repair and G2 arrest capacity after exposure to either 2 or 4 Gy. Our study confirms that haploinsufficiency is the mechanism involved in radiosensitivity in patients with a PTC allele, but it suggests that further research is needed to evaluate alternative mechanisms for mutations not subjected to NMD

Stress corrosion cracking in Al-Zn-Mg-Cu aluminum alloys in saline environments

Copyright 2013 ASM International. This paper was published in Metallurgical and Materials Transactions A, 44A(3), 1230 - 1253, and is made available as an electronic reprint with the permission of ASM International. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplications of any material in this paper for a fee or for commercial purposes, or modification of the content of this paper are prohibited.Stress corrosion cracking of Al-Zn-Mg-Cu (AA7xxx) aluminum alloys exposed to saline environments at temperatures ranging from 293 K to 353 K (20 °C to 80 °C) has been reviewed with particular attention to the influences of alloy composition and temper, and bulk and local environmental conditions. Stress corrosion crack (SCC) growth rates at room temperature for peak- and over-aged tempers in saline environments are minimized for Al-Zn-Mg-Cu alloys containing less than ~8 wt pct Zn when Zn/Mg ratios are ranging from 2 to 3, excess magnesium levels are less than 1 wt pct, and copper content is either less than ~0.2 wt pct or ranging from 1.3 to 2 wt pct. A minimum chloride ion concentration of ~0.01 M is required for crack growth rates to exceed those in distilled water, which insures that the local solution pH in crack-tip regions can be maintained at less than 4. Crack growth rates in saline solution without other additions gradually increase with bulk chloride ion concentrations up to around 0.6 M NaCl, whereas in solutions with sufficiently low dichromate (or chromate), inhibitor additions are insensitive to the bulk chloride concentration and are typically at least double those observed without the additions. DCB specimens, fatigue pre-cracked in air before immersion in a saline environment, show an initial period with no detectible crack growth, followed by crack growth at the distilled water rate, and then transition to a higher crack growth rate typical of region 2 crack growth in the saline environment. Time spent in each stage depends on the type of pre-crack (“pop-in” vs fatigue), applied stress intensity factor, alloy chemistry, bulk environment, and, if applied, the external polarization. Apparent activation energies (E a) for SCC growth in Al-Zn-Mg-Cu alloys exposed to 0.6 M NaCl over the temperatures ranging from 293 K to 353 K (20 °C to 80 °C) for under-, peak-, and over-aged low-copper-containing alloys (~0.8 wt pct), they are typically ranging from 20 to 40 kJ/mol for under- and peak-aged alloys, and based on limited data, around 85 kJ/mol for over-aged tempers. This means that crack propagation in saline environments is most likely to occur by a hydrogen-related process for low-copper-containing Al-Zn-Mg-Cu alloys in under-, peak- and over-aged tempers, and for high-copper alloys in under- and peak-aged tempers. For over-aged high-copper-containing alloys, cracking is most probably under anodic dissolution control. Future stress corrosion studies should focus on understanding the factors that control crack initiation, and insuring that the next generation of higher performance Al-Zn-Mg-Cu alloys has similar longer crack initiation times and crack propagation rates to those of the incumbent alloys in an over-aged condition where crack rates are less than 1 mm/month at a high stress intensity factor

ARM-CO-UP: ARM COoperative Utilization of Processors

HMPSoCs combine different processors on a single chip. They enable powerful embedded devices, which increasingly perform ML inference tasks at the edge. State-of-the-art HMPSoCs can perform on-chip embedded inference using different processors, such as CPUs, GPUs, and NPUs. HMPSoCs can potentially overcome the limitation of low single-processor CNN inference performance and efficiency by cooperative use of multiple processors. However, standard inference frameworks for edge devices typically utilize only a single processor.We present the ARM-CO-UP framework built on the ARM-CL library. The ARM-CO-UP framework supports two modes of operation – Pipeline and Switch. It optimizes inference throughput using pipelined execution of network partitions for consecutive input frames in the Pipeline mode. It improves inference latency through layer-switched inference for a single input frame in the Switch mode. Furthermore, it supports layer-wise CPU/GPU DVFS in both modes for improving power efficiency and energy consumption. ARM-CO-UP is a comprehensive framework for multi-processor CNN inference that automates CNN partitioning and mapping, pipeline synchronization, processor type switching, layer-wise DVFS, and closed-source NPU integration

CPU-GPU Layer-Switched Low Latency CNN Inference

Convolutional Neural Networks (CNNs) inference on Heterogeneous Multi-Processor System-on-Chips (HMPSoCs) in edge devices represent cutting-edge embedded machine learning. Embedded CPU and GPU within an HMPSoC can both perform inference using CNNs. However, common practice is to run a CNN on the HMPSoC component (CPU or GPU) provides the best performance (lowest latency) for that CNN. CNNs are not monolithic and are composed of several layers of different types. Some of these layers have lower latency on the CPU, while others execute faster on the GPU. In this work, we investigate the reason behind this observation. We also propose an execution of CNN that switches between CPU and GPU at the layer granularity, wherein a CNN layer executes on the component that provides it with the lowest latency. Switching between the CPU and the GPU back and forth mid-inference introduces additional overhead (delay) in the inference. Regardless of overhead, we show in this work that a CPU-GPU layer switched execution results in, on average, having 4.72% lower CNN inference latency on the Khadas VIM 3 board with Amlogic A311D HMPSoC

3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems

The heat produced during computation severely limits the performance of multi-/many-core processors. High-performance 3D-stacked processor-memory systems stack cores and main memory on a single die. However, 3D-stacked systems suffer more severe thermal issues than their non-stacked planar 2D counterparts. Consequently, the aggressive thermal throttling required for their thermally-safe operation limits the potential performance gains. Power budgeting is an effective thermal management technique that prevents thermal throttling in multi-/many-core processors by assigning a thermally-safe power budget to cores within the processors. State-of-the-art power budgeting techniques for 2D processors do not account for the vertical thermal coupling between the layers of the 3D-stacked system and will fail to prevent thermal throttling in them. Furthermore, estimating thermals for a 3D-stacked processor with power budgeting requires a finer-grained RC thermal model than non-stacked processors. This requirement inhibits the porting of existing power budgeting solutions for 2D processors to 3D-stacked processor-memory systems. This work is the first to present the linear algebra-based algorithmic time-invariant transformations required to enable power budgeting in 3D-stacked systems. Based on the transformations, we propose the first transient-temperature-aware power budgeting technique, 3D-TTP, for 3D-stacked systems. Detailed interval thermal simulations with the advanced CoMeT simulator designed for 3D-stacked systems also confirm no thermal violations with our 3D-TTP technique. 3D-TTP exhibits an average 11.41% speedup over the state-of-the-art reactive-based thermal management technique

miR-132/212 knockout mice reveal roles for these miRNAs in regulating cortical synaptic transmission and plasticity

miR-132 and miR-212 are two closely related miRNAs encoded in the same intron of a small non-coding gene, which have been suggested to play roles in both immune and neuronal function. We describe here the generation and initial characterisation of a miR-132/212 double knockout mouse. These mice were viable and fertile with no overt adverse phenotype. Analysis of innate immune responses, including TLR-induced cytokine production and IFNβ induction in response to viral infection of primary fibroblasts did not reveal any phenotype in the knockouts. In contrast, the loss of miR-132 and miR-212, while not overtly affecting neuronal morphology, did affect synaptic function. In both hippocampal and neocortical slices miR-132/212 knockout reduced basal synaptic transmission, without affecting paired-pulse facilitation. Hippocampal long-term potentiation (LTP) induced by tetanic stimulation was not affected by miR-132/212 deletion, whilst theta burst LTP was enhanced. In contrast, neocortical theta burst-induced LTP was inhibited by loss of miR-132/212. Together these results indicate that miR-132 and/or miR-212 play a significant role in synaptic function, possibly by regulating the number of postsynaptic AMPA receptors under basal conditions and during activity-dependent synaptic plasticity

Αξιολόγηση εξωτερικοτήτων εγκαταστάσεων βιοαερίου

Fusarium oxysporum f. sp. cubense tropical race 4 (TR4) is reported for the first time in northern Queensland, the centre of Australia’s commercial banana production. The identity of the pathogen was confirmed by vegetative compatibility group testing, TR4 specific PCR tests and sequencing. Although presently confined to a single property, the disease poses a serious threat to Australia’s banana industry

Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations

On-chip thermal management is quintessential to a thermally safe operation of a many-core processor. The presence of a physically distributed logically shared Last-Level Cache (LLC) significantly reduces the performance penalty of migrating threads within the cores of an S-NUCA many-core. This cost reduction allows novel thermal management of these many-cores via synchronous thread migration. Synchronous thread migration provides a viable alternative to Dynamic Voltage and Frequency Scaling (DVFS) and asynchronous thread migration used traditionally to manage thermals of S-NUCA many-cores. We present a theoretical method to compute the peak tem-perature in many-cores with synchronous thread migrations. We use the method to create a thermal management heuristic called HotPotato that maximizes the performance of S-NUCA many-cores under a peak temperature constraint. We implement HotPotato within the state-of-the-art HotSniper simulator. Detailed interval thermal simulations with HotSniper show an average 10.72% improvement in response time of S-NUCA many-cores when scheduling with HotPotato compared to a state-of-the-art thermal-aware S-NUCA scheduler

PELSI: Power-Efficient Layer-Switched Inference

Convolutional Neural Networks (CNNs) are now quintessential kernels within embedded computer vision applications deployed in edge devices. Heterogeneous Multi-Processor System-on-Chips (HMPSoCs) with Dynamic Voltage and Frequency Scaling (DVFS) capable components (CPUs and GPUs) allow for low-latency, low-power CNN inference on resource-constrained edge devices when employed efficiently. CNNs comprise several heterogeneous layer types that execute with different degrees of power efficiency on different HMPSoC components at different frequencies. We propose the first framework, PELSI, that exploits this layer-wise power efficiency heterogeneity for power-efficient CPU-GPU layer-switched CNN interference on HMPSoCs. PELSI executes each layer of a CNN on an HMPSoC component (CPU or GPU) clocked at just the right frequency for every layer such that the CNN meets its inference latency target with minimal power consumption while still accounting for the power-performance overhead of multiple switching between CPU and GPU mid-inference. PELSI incorporates a Genetic Algorithm (GA) to identify the near-optimal CPU-GPU layer-switched CNN inference configuration from within the large exponential design space that meets the given latency requirement most power efficiently. We evaluate PELSI on Rock-Pi embedded platform. The platform contains an RK3399Pro HMPSoC with DVFS-capable CPU clusters and GPU. Empirical evaluations with five different CNNs show a 44.48% improvement in power efficiency for CNN inference under PELSI over the state-of-the-art