Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial $180$ nm HV-CMOS process and contains a matrix of $128\times128$ square pixels with $25$ $\mu$m pitch. First prototypes have been produced with a standard resistivity of $\sim20$ $\Omega$cm for the substrate and tested in standalone mode. The results show a rise time of $\sim20$ ns, charge gain of $190$ mV/ke$^{-}$ and $\sim40$ e$^{-}$ RMS noise for a power consumption of $4.8$ $\mu$W/pixel. The main design aspects, as well as standalone measurement results, are presented.Comment: 13 pages, 13 figures, 2 tables. Work carried out in the framework of the CLICdp collaboratio

Actividad eléctrica muscular en la marcha a distintas velocidades y en la carrera

En este estudio se analiza la actividad electromiográfica de los principales músculos de la extremidad inferior derecha: Glúteos Mayor y Medio, Recto Anterior y Vasto Interno del Cuádriceps, Isquiotibioperoneos, Gemelos y Tibial Anterior, al caminar en un tapiz rodante a distintas velocidades y en una carrera suave. Para dividir el ciclo de la marcha y la carrera en fases se utilizó un sistema de análisis tridimensional con dos cámaras de vídeo. La señal electromiográfica de cada una de estas fases se integró y se expresó en porcentaje de la actividad máxima isométrica de su músculo correspondiente. Los resultados obtenidos muestran que la participación muscular en la marcha lenta y normal es muy similar, sin embargo, en la marcha rápida aparecen aumentos importantes conservando el mismo patrón de actuación. En la carrera, no sólo existen actividades del triple de las halladas en la marcha a velocidad cómoda, sino que se modifica el patrón de actuación, presentando todos los músculos sus picos de actividad durante la fase de apoyo, momento en el que el centro de gravedad se lleva hacia delante sobre el miembro inferior

Actividad eléctrica muscular en la marcha a distintas velocidades y en la carrera

En este estudio se analiza la actividad electromiográfica de los principales músculos de la extremidad inferior derecha: Glúteos Mayor y Medio, Recto Anterior y Vasto Interno del Cuádriceps, Isquiotibioperoneos, Gemelos y Tibial Anterior, al caminar en un tapiz rodante a distintas velocidades y en una carrera suave. Para dividir el ciclo de la marcha y la carrera en fases se utilizó un sistema de análisis tridimensional con dos cámaras de vídeo. La señal electromiográfica de cada una de estas fases se integró y se expresó en porcentaje de la actividad máxima isométrica de su músculo correspondiente. Los resultados obtenidos muestran que la participación muscular en la marcha lenta y normal es muy similar, sin embargo, en la marcha rápida aparecen aumentos importantes conservando el mismo patrón de actuación. En la carrera, no sólo existen actividades del triple de las halladas en la marcha a velocidad cómoda, sino que se modifica el patrón de actuación, presentando todos los músculos sus picos de actividad durante la fase de apoyo, momento en el que el centro de gravedad se lleva hacia delante sobre el miembro inferior

Medipix3 Demonstration and understanding of near ideal detector performance for 60 & 80 keV electrons

In our article we report first quantitative measurements of imaging performance for the current generation of hybrid pixel detector, Medipix3, as direct electron detector. Utilising beam energies of 60 & 80 keV, measurements of modulation transfer function (MTF) and detective quantum efficiency (DQE) have revealed that, in single pixel mode (SPM), energy threshold values can be chosen to maximize either the MTF or DQE, obtaining values near to, or even exceeding, those for an ideal detector. We have demonstrated that the Medipix3 charge summing mode (CSM) can deliver simultaneous, near ideal values of both MTF and DQE. To understand direct detection performance further we have characterized the detector response to single electron events, building an empirical model which can predict detector MTF and DQE performance based on energy threshold. Exemplifying our findings we demonstrate the Medipix3 imaging performance, recording a fully exposed electron diffraction pattern at 24-bit depth and images in SPM and CSM modes. Taken together our findings highlight that for transmission electron microscopy performed at low energies (energies <100 keV) thick hybrid pixel detectors provide an advantageous and alternative architecture for direct electron imagin

FastIC: a fast integrated circuit for the readout of high performance detectors

This work presents the 8-channel FastIC ASIC developed in CMOS 65 nm technology suitable for the readout of positive and negative polarity sensors in high energy physics experiments, Cherenkov detectors and time-of-flight systems. The front-end can be configured to perform analog summation of up to 4 single-ended channels before discrimination in view of improving time resolution when segmenting a SiPM. The outputs encode the time-of-arrival information and linear energy measurement which captures the peak amplitude of the input signal in the 5 µA–25 mA input peak current range. Power consumption of the ASIC is 12 mW/ch with default settings. Measurements of single photon time resolution with a red-light laser source and a HPK SiPM S13360-3050CS are ≈140 ps FWHM

20-ps resolution Clock Distribution Network for a fast-timing single photon detector

The time resolution of active pixel sensors whose timestamp mechanism is based on Time-to-Digital Converters is critically linked to the accuracy in the distribution of the master clock signal that latches the timestamp values across the detector. The Clock Distribution Network that delivers the master clock signal must compensate process-voltage-temperature variations to reduce static time errors (skew), and minimize the power supply bounce to prevent dynamic time errors (jitter). To achieve sub-100ps time resolution within pixel detectors and thus enable a step forward in multiple imaging applications, the network latencies must be adjusted in steps well below that value. Power consumption must be kept as low as possible. In this work, a self-regulated Clock Distribution Network that fulfills these requirements is presented for the FastICpix single photon detector ¿ aiming at a 65nm process. A 40 MHz master clock is distributed to 64x64 pixels over an area of 2.4x2.4 cm2 using digital Delay-Locked Loops, achieving clock leaf skew below 20 ps with a power consumption of 26 mW. Guidelines are provided to adapt the system to arbitrary chip area and pixel pitch values, yielding a versatile design with very fine time resolution

Design and characterisation of the CLICTD pixelated monolithic sensor chip

A novel monolithic pixelated sensor and readout chip, the CLIC Tracker Detector (CLICTD) chip, is presented. The CLICTD chip was designed targeting the requirements of the silicon tracker development for the experiment at the Compact Linear Collider (CLIC), and has been fabricated in a modified 180 nm CMOS imaging process with charge collection on a high-resistivity p-type epitaxial layer. The chip features a matrix of 16×128 elongated channels, each measuring 300×30 μm2. Each channel contains 8 equidistant collection electrodes and analog readout circuits to ensure prompt signal formation. A simultaneous 8-bit Time-of-Arrival (with 10 ns time bins) and 5-bit Time-over-Threshold measurement is performed on the combined digital output of the 8 sub-pixels in every channel. The chip has been fabricated in two process variants and characterised in laboratory measurements using electrical test pulses and radiation sources. Results show a minimum threshold between 135 and 180 e‾ and a noise of about 14 e‾ RMS. The design aspects and characterisation results of the CLICTD chip are presented

The GBT Project

The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planned for the SLHC, the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs address this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between the counting room and the experiments. The paper describes in detail the GBT-SERDES architecture and presents an overview of the various components that constitute the GBT chipset