Automated system to measure the carbonate concentration of sediments

We have developd a computer controlled system to measure the calcium carbonate content of sediment samples. A menu driven program controls the analysis of each sample. The system first communicates with a Mettler digital balance to record the weights of the 40 samples which must be loaded into each run. The sample boats are next loaded into the sample carousel which is then sealed from the atmosphere. The system is first pumped down to a vacuum of 0.04 torr. The valve to the pump closes and the stepping motor turns the carousel, moving a sample boat over the delivery slot and dropping the sample into 80°C 100% phosphoric acid under vigorous spinning action. During the reaction, carbonate is evolved into H2O and CO2 and the resulting pressure change within the closed system is measured by a pressure transducer and recorded into memory next to the sample identification and sample weight. The system is pumped once again to 0.04 torr and the process continues until all 40 samples have been analyzed. The data can then be uploaded and converted to percent carbonate values using a regression line produced from multiple analyses of varying weights of a 100% carbonate standard. Precision of the system, based upon 120 replicate analysis ranges from 0.49% to 0.88%.Funding was provided by the National Science Foundation through Grant Nos. OCE 85-11014 and OCE 88-13307

A rocket-borne microprocessor-based experiment for investigation of energetic particles in the D and E regions

An energetic experiment using the Z80 family of microcomputer components is described. Data collected from the experiment allowed fast and efficient postprocessing, yielding both energy-spectrum and pitch-angle distribution of energetic particles in the D and E regions. Advanced microprocessor system architecture and software concepts were used in the design to cope with the large amount of data being processed. This required the Z80 system to operate at over 80% of its total capacity. The microprocessor system was included in the payloads of three rockets launched during the Energy Budget Campaign at ESRANGE, Kiruna, Sweden in November 1980. Based on preliminary examination of the data, the performance of the experiment was satisfactory and good data were obtained on the energy spectrum and pitch-angle distribution of the particles

Study of the Impact of Hardware Failures on Software Reliability

Software plays an increasingly important role in modern safety-critical systems. Reliable software becomes desirable for all stakeholders. Typical software related failures include software internal failures, input failures, output failures, support failures and multiple interaction failures. This dissertation provides a methodology to study the impact of hardware support failures on software reliability. The hardware failures we are focusing on in this study are semiconductor device intrinsic failures that are directly related to software execution during device operation. The software execution on hardware devices, in essence, is a series of 0 and 1 signal alternations for the inputs of hardware components. Such signal alternations lead to voltage changes and current flows in the microelectronic hardware device, which serve as electrical stresses on the device and may lead to physical failures. The failure mechanisms include Hot Carrier Injection (HCI), Electromigration (EM), and Time Dependent Dielectric Breakdown (TDDB). During device operation such hardware failures could propagate to circuit level in the form of signal delays, changes of circuit functionality, and signals stuck at a logic value (0 or 1), which could further propagate into the software layer and affect the reliability of the software. The proposed methodology is divided into three parts: (i) analysis of the manifestations of permanent failures on circuit elements (logic gates, flip-flops, etc.), (ii) development of reliability models for the circuit elements as functions of the software execution, and (iii) calculation of failure probability distributions of the hardware circuit elements under the software execution. The methodology is applied to a comprehensive case study, targeting all the CPU registers and ALU logic gates of a computer system based on the Z80 microprocessor. About 120 different types of failure manifestations are observed, and more than 250 reliability models for the different types of failure manifestations and circuit elements are developed. Such models allow us to calculate the failure probability distributions of the CPU registers and ALU gates of the Z80 computer system under the software execution. We also extend the methodology and the case study to the consideration of transient failures, also known as Single Event Upsets (SEUs)

Teknik mikroprosesor untuk SMK/MAK Kelas X - Semester 2

Penyajian buku teks untuk disusun dengan tujuan agar peserta didik dapat melakukan proses pencarian pengetahuan berkenaan dengan materi pelajaran melalui berbagai aktivitas para ilmuwan dalam melakukan eksperimen, dengan demikian peserta didik diarahkan untuk menemukan sendiri berbagai fakta, membangun konsep, dan nilai-nilai baru secara mandir

Design of microprocessor-based hardware for number theoretic transform implementation

Number Theoretic Transforms (NTTs) are defined in a finite ring of integers Z (_M), where M is the modulus. All the arithmetic operations are carried out modulo M. NTTs are similar in structure to DFTs, hence fast FFT type algorithms may be used to compute NTTs efficiently. A major advantage of the NTT is that it can be used to compute error free convolutions, unlike the FFT it is not subject to round off and truncation errors. In 1976 Winograd proposed a set of short length DFT algorithms using a fewer number of multiplications and approximately the same number of additions as the Cooley-Tukey FFT algorithm. This saving is accomplished at the expense of increased algorithm complexity. These short length DFT algorithms may be combined to perform longer transforms. The Winograd Fourier Transform Algorithm (WFTA) was implemented on a TMS9900 microprocessor to compute NTTs. Since multiplication conducted modulo M is very time consuming a special purpose external hardware modular multiplier was designed, constructed and interfaced with the TMS9900 microprocessor. This external hardware modular multiplier allowed an improvement in the transform execution time. Computation time may further be reduced by employing several microprocessors. Taking advantage of the inherent parallelism of the WFTA, a dedicated parallel microprocessor system was designed and constructed to implement a 15-point WFTA in parallel. Benchmark programs were written to choose a suitable microprocessor for the parallel microprocessor system. A master or a host microprocessor is used to control the parallel microprocessor system and provides an interface to the outside world. An analogue to digital (A/D) and a digital to analogue (D/A) converter allows real time digital signal processing

Design of components for a generic microprocessor architecture

The objective of this thesis was to develop a generic microprocessor design that can be adapted to many of the existing 16 bit microprocessors. Common features of various microprocessors were used to develop the design of many generic components which can then be used to design the required microprocessors instead of custom-designing each one of them separately. The components were designed using a CISC based micro-programmed design approach as that was more suitable in terms of design and verification time for generic implementation. The generic parts designed include the Register File for temporary data storage, the Effective Address Calculator that generates the effective address for the operand, the Barrel Shifter for fast multiply/divide operations and the Priority Encoder for determining the processor state