38 research outputs found
Studies on Core-Based Testing of System-on-Chips Using Functional Bus and Network-on-Chip Interconnects
The tests of a complex system such as a microprocessor-based system-onchip
(SoC) or a network-on-chip (NoC) are difficult and expensive. In this thesis,
we propose three core-based test methods that reuse the existing functional
interconnects-a flat bus, hierarchical buses of multiprocessor SoC's (MPSoC),
and a N oC-in order to avoid the silicon area cost of a dedicated test access mechanism
(TAM). However, the use of functional interconnects as functional TAM's
introduces several new problems.
During tests, the interconnects-including the bus arbitrator, the bus bridges,
and the NoC routers-operate in the functional mode to transport the test stimuli
and responses, while the core under tests (CUT) operate in the test mode. Second,
the test data is transported to the CUT through the functional bus, and not
directly to the test port. Therefore, special core test wrappers that can provide
the necessary control signals required by the different functional interconnect are
proposed. We developed two types of wrappers, one buffer-based wrapper for the
bus-based systems and another pair of complementary wrappers for the NoCbased
systems.
Using the core test wrappers, we propose test scheduling schemes for the three
functionally different types of interconnects. The test scheduling scheme for a flat
bus is developed based on an efficient packet scheduling scheme that minimizes
both the buffer sizes and the test time under a power constraint. The schedulingscheme is then extended to take advantage of the hierarchical bus architecture of
the MPSoC systems. The third test scheduling scheme based on the bandwidth
sharing is developed specifically for the NoC-based systems. The test scheduling
is performed under the objective of co-optimizing the wrapper area cost and the
resulting test application time using the two complementary NoC wrappers.
For each of the proposed methodology for the three types of SoC architec ..
ture, we conducted a thorough experimental evaluation in order to verify their
effectiveness compared to other methods
SoC Test: Trends and Recent Standards
The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper
Design for pre-bond testability in 3D integrated circuits
In this dissertation we propose several DFT techniques specific to 3D
stacked IC systems. The goal has explicitly been to create techniques that
integrate easily with existing IC test systems. Specifically, this means
utilizing scan- and wrapper-based techniques, two foundations
of the digital IC test industry.
First, we describe a general test architecture for 3D ICs. In this
architecture, each tier of a 3D design is wrapped in test control logic that
both manages tier test
pre-bond and integrates the tier into the large test architecture post-bond.
We describe a new kind of boundary scan to provide the necessary test control
and observation of the partial circuits, and we propose
a new design methodology for test hardcore that ensures both pre-bond functionality
and post-bond optimality. We present the application of these techniques to
the 3D-MAPS test vehicle, which has proven their effectiveness.
Second, we extend these DFT techniques to circuit-partitioned designs. We find
that boundary scan design is generally sufficient, but that some 3D designs require
special DFT treatment. Most importantly, we demonstrate that the functional
partitioning inherent in 3D design can potentially decrease the total test cost
of verifying a circuit.
Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm
co-designs the pre-bond and post-bond wrappers to simultaneously minimize test
time and routing cost. On average, our algorithm utilizes over 90% of the wires
in both the pre-bond and post-bond wrappers.
Finally, we look at the 3D vias themselves to develop a low-cost, high-volume
pre-bond test methodology appropriate for production-level test. We describe
the shorting probes methodology, wherein large test probes are used to contact
multiple small 3D vias. This technique is an all-digital test method that
integrates seamlessly into existing test flows. Our
experimental results demonstrate two key facts: neither the large capacitance
of the probe tips nor the process variation in the 3D vias and the probe tips
significantly hinders the testability of the circuits.
Taken together, this body of work defines a complete test methodology for
testing 3D ICs pre-bond, eliminating one of the key hurdles to the
commercialization of 3D technology.PhDCommittee Chair: Lee, Hsien-Hsin; Committee Member: Bakir, Muhannad; Committee Member: Lim, Sung Kyu; Committee Member: Vuduc, Richard; Committee Member: Yalamanchili, Sudhaka
Design-for-delay-testability techniques for high-speed digital circuits
The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud
getting more and more important
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p>Dissertatio
Elastic bundles :modelling and architecting asynchronous circuits with granular rigidity
PhD ThesisIntegrated Circuit (IC) designs these days are predominantly System-on-Chips (SoCs).
The complexity of designing a SoC has increased rapidly over the years due to growing
process and environmental variations coupled with global clock distribution di culty.
Moreover, traditional synchronous design is not apt to handle the heterogeneous timing
nature of modern SoCs. As a countermeasure, the semiconductor industry witnessed
a strong revival of asynchronous design principles. A new paradigm of digital circuits
emerged, as a result, namely mixed synchronous-asynchronous circuits. With a wave
of recent innovations in synchronous-asynchronous CAD integration, this paradigm is
showing signs of commercial adoption in future SoCs mainly due to the scope for reuse
of synchronous functional blocks and IP cores, and the co-existence of synchronous and
asynchronous design styles in a common EDA framework.
However, there is a lack of formal methods and tools to facilitate mixed synchronousasynchronous
design. In this thesis, we propose a formal model based on Petri nets with
step semantics to describe these circuits behaviourally. Implication of this model in the
veri cation and synthesis of mixed synchronous-asynchronous circuits is studied. Till
date, this paradigm has been mainly explored on the basis of Globally Asynchronous
Locally Synchronous (GALS) systems. Despite decades of research, GALS design has
failed to gain traction commercially. To understand its drawbacks, a simulation framework
characterising the physical and functional aspects of GALS SoCs is presented.
A novel method for synthesising mixed synchronous-asynchronous circuits with varying
levels of rigidity is proposed. Starting with a high-level data ow model of a system which
is intrinsically asynchronous, the key idea is to introduce rigidity of chosen granularity
levels in the model without changing functional behaviour. The system is then partitioned
into functional blocks of synchronous and asynchronous elements before being transformed
into an equivalent circuit which can be synthesised using standard EDA tools
Network-on-Chip
Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoCâits research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems
Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
Accessing embedded test and monitoring circuitry (the so-called embedded instruments) in in-field products can reduce maintenance and diagnostics costs. Performing such access can be facilitated when done over an internal system bus, due to that it might be faster and less cumbersome to reach a system processor (on an in-field product) over a network interface, compared with the effort and speed of gaining access to a test interface on the same product. Enabling such access might require that, at the component level, the embedded instruments in a system-on-chip (SoC) become accessible both from a chip interface and from an on-chip processor over a system bus. Although this reuse of embedded instruments can be achieved by already existing standards, such as IEEE 1687, the system bus might become a scalability bottleneck when the number of instruments that are to be reused increases. In this paper, we propose two solutions that address the scalability in this type of reuse while maintaining compatibility with IEEE 1687 tools. We also discuss the trade-offs associated with each approach and present timing analyses that by considering system parameters such as clock rates determine how the correct operation can be guaranteed. To validate the proposed solutions, we have implemented them on an FPGA using AXI as system bus, and have used standard IEEE 1687 tools to access the instruments. We present some details of the implementation to highlight practical issues such as clock domain crossing, as well as how the presented timing analyses can be used to adjust design parameters
Communication synthesis of networks-on-chip (NoC)
The emergence of networks-on-chip (NoC) as the communication infrastructure solution
for complex multi-core SoCs presents communication synthesis challenges. This
dissertation addresses the design and run-time management aspects of communication
synthesis. Design reuse and the infeasibility of Intellectual Property (IP) core
interface redesign, requires the development of a Core-Network Interface (CNI) which
allows them to communicate over the on-chip network. The absence of intelligence
amongst the NoC components, entails the introduction of a CNI capable of not only
providing basic packetization and depacketization, but also other essential services
such as reliability, power management, reconguration and test support. A generic
CNI architecture providing these services for NoCs is proposed and evaluated in this
dissertation.
Rising on-chip communication power costs and reliability concerns due to these,
motivate the development of a peak power management technique that is both scalable
to dierent NoCs and adaptable to varying trac congurations. A scalable
and adaptable peak power management technique - SAPP - is proposed and demonstrated.
Latency and throughput improvements observed with SAPP demonstrate its
superiority over existing techniques.
Increasing design complexity make prediction of design lifetimes dicult. Post SoC deployment, an on-line health monitoring scheme, is essential to maintain con-
dence in the correct operation of on-chip cores. The rising design complexity and
IP core test costs makes non-concurrent testing of the IP cores infeasible. An on-line
scheme capable of managing IP core test in the presence of executing applications is
essential. Such a scheme ensures application performance and system power budgets
are eciently managed. This dissertation proposes Concurrent On-Line Test (COLT)
for NoC-based systems and demonstrates how a robust implementation of COLT using
a Test Infrastructure-IP (TI-IP) can be used to maintain condence in the correct
operation of the SoC