On the Robustness of Deep Learning-predicted Contention Models for Network Calculus

The network calculus (NC) analysis takes a simple model consisting of a network of schedulers and data flows crossing them. A number of analysis "building blocks" can then be applied to capture the model without imposing pessimistic assumptions like self-contention on tandems of servers. Yet, adding pessimism cannot always be avoided. To compute the best bound on a single flow's end-to-end delay thus boils down to finding the least pessimistic contention models for all tandems of schedulers in the network - and an exhaustive search can easily become a very resource intensive task. The literature proposes a promising solution to this dilemma: a heuristic making use of machine learning (ML) predictions inside the NC analysis. While results of this work were promising in terms of delay bound quality and computational effort, there is little to no insight on when a prediction is made or if the trained algorithm can achieve similarly striking results in networks vastly differing from its training data. In this paper, we address these pending questions. We evaluate the influence of the training data and its features on accuracy, impact and scalability. Additionally, we contribute an extension of the method by predicting the best $n$ contention model alternatives in order to achieve increased robustness for its application outside the training data. Our numerical evaluation shows that good accuracy can still be achieved on large networks although we restrict the training to networks that are two orders of magnitude smaller

Beyond the Accuracy-Complexity Tradeoffs of Compositional Analyses using Network Calculus for Complex Networks

Achieving the accuracy-complexity tradeoffs for compositional timing analyses using Network Calculus is still a hot research topic. In this specific area, we propose in this paper an improved version of the Total Flow Analysis (TFA) algorithm, called TFA++, when taking into account the impact of the finite transmission capacity of the network links on the input and output traffic models at each network node. First, we review the existing analysis algorithms by identifying their main limitations in terms of accuracy and complexity, through a simple but representative network example. Afterwards, we define the TFA++ algorithm and we detail the main steps of the followed methodology to compute the delay upper bounds. Moreover, we conduct comparative analyses of the derived delay bounds and analysis times with the different algorithms, with respect to the network size and load. In doing this, we highlight noticeable enhancements of both metrics under TFA++, in comparison to the existing algorithms; thus the high accuracy and low complexity of TFA++. Finally, this statement has been asserted through a representative avionics case

Quantitative Performance Comparison of Various Traffic Shapers in Time-Sensitive Networking

Owning to the sub-standards being developed by IEEE Time-Sensitive Networking (TSN) Task Group, the traditional IEEE 802.1 Ethernet is enhanced to support real-time dependable communications for future time- and safety-critical applications. Several sub-standards have been recently proposed that introduce various traffic shapers (e.g., Time-Aware Shaper (TAS), Asynchronous Traffic Shaper (ATS), Credit-Based Shaper (CBS), Strict Priority (SP)) for flow control mechanisms of queuing and scheduling, targeting different application requirements. These shapers can be used in isolation or in combination and there is limited work that analyzes, evaluates and compares their performance, which makes it challenging for end-users to choose the right combination for their applications. This paper aims at (i) quantitatively comparing various traffic shapers and their combinations, (ii) summarizing, classifying and extending the architectures of individual and combined traffic shapers and their Network calculus (NC)-based performance analysis methods and (iii) filling the gap in the timing analysis research on handling two novel hybrid architectures of combined traffic shapers, i.e., TAS+ATS+SP and TAS+ATS+CBS. A large number of experiments, using both synthetic and realistic test cases, are carried out for quantitative performance comparisons of various individual and combined traffic shapers, from the perspective of upper bounds of delay, backlog and jitter. To the best of our knowledge, we are the first to quantitatively compare the performance of the main traffic shapers in TSN. The paper aims at supporting the researchers and practitioners in the selection of suitable TSN sub-protocols for their use cases

nDimNoC: Real-Time D-dimensional NoC

The growing demand of powerful embedded systems to perform advanced functionalities led to a large increase in the number of computation nodes integrated in Systems-on-chip (SoC). In this context, network-on-chips (NoCs) emerged as a new standard communication infrastructure for multi-processor SoCs (MPSoCs). In this work, we present nDimNoC, a new D-dimensional NoC that provides real-time guarantees for systems implemented upon MPSoCs. Specifically, (1) we propose a new router architecture and a new deflection-based routing policy that use the properties of circulant topologies to ensure bounded worst-case communication delays, and (2) we develop a generic worst-case communication time (WCCT) analysis for packets transmitted over nDimNoC. In our experiments, we show that the WCCT of packets decreases when we increase the dimensionality of the NoC using nDimNoC 19s topolgy and routing policy. By implementing nDimNoC in Verilog and synthesizing it for an FPGA platform, we show that a 3D-nDimNoC requires "485-times less silicon than routers that use virtual channels (VC). We computed the maximum operating frequency of a 3D-nDimNoC with Xilinx Vivado. Increasing the number dimensions in the NoC improves WCCT at the cost of a more complex routing logic that may result in a reduced operating clock frequency.info:eu-repo/semantics/publishedVersio

On Cyclic Dependencies and Regulators in Time-Sensitive Networks

For time-sensitive networks, as in the context of IEEE TSN and IETF Detnet, cyclic dependencies are associated with certain fundamental properties such as improving availability and decreasing reconfiguration effort. Nevertheless, the existence of cyclic dependencies can cause very large latency bounds or even global instability, thus making the proof of the timing predictability of such networks a much more challenging issue. Cyclic dependencies can be removed by reshaping flows inside the network, by means of regulators. We consider FIFO-per-class networks with two types of regulators: perflow regulators and interleaved regulators (the latter reshape entire flow aggregates). Such regulators come with a hardware cost that is less for an interleaved regulator than for a perflow regulator; both can affect the latency bounds in different ways. We analyze the benefits of both types of regulators in partial and full deployments in terms of latency. First, we propose Low-Cost Acyclic Network (LCAN), a new algorithm for finding the optimum number of regulators for breaking all cyclic dependencies. Then, we provide another algorithm, Fixed- Point Total Flow Analysis (FP-TFA), for computing end-to-end delay bounds for general topologies, i.e., with and without cyclic dependencies. An extensive analysis of these proposed algorithms was conducted on generic grid topologies. For these test networks, we find that FP-TFA computes small latency bounds; but, at a medium to high utilization, the benefit of regulators becomes apparent. At high utilization or for high line transmission-rates, a small number of per-flow regulators has an effect on the latency bound larger than a small number of interleaved regulators. Moreover, interleaved regulators need to be placed everywhere in the network to provide noticeable improvements. We validate the applicability of our approaches on a realistic industrial timesensitive network

Worst-Case Timing Analysis of AeroRing- A Full Duplex Ethernet Ring for Safety-critical Avionics

Avionics implementation with less cables will clearly improve the efficiency of aircraft while reducing weight and maintenance costs. To fulfill these emerging needs, an innovative avionics communication architecture, based on Gigabit Full Duplex Ethernet ring, is proposed in this paper. To adapt this COTS technology to safety-critical avionics, an adequate tuning process of the communication protocol and the choice of reliability mechanisms to achieve timely and reliable communications are first detailed. Then, efficient timing analyses of such a proposal based on Network Calculus are conducted, accounting the impact of a ring topology and the specified reliability mechanisms. Third, these general analyses are illustrated in the case of a realistic avionic application, to replace the AFDX backup network with AeroRing, to reduce wires, while guaranteeing timely communications

Studies of Uncertainties in Smart Grid: Wind Power Generation and Wide-Area Communication

This research work investigates the uncertainties in Smart Grid, with special focus on the uncertain wind power generation in wind energy conversion systems (WECSs) and the uncertain wide-area communication in wide-area measurement systems (WAMSs). For the uncertain wind power generation in WECSs, a new wind speed modeling method and an improved WECS control method are proposed, respectively. The modeling method considers the spatial and temporal distributions of wind speed disturbances and deploys a box uncertain set in wind speed models, which is more realistic for practicing engineers. The control method takes maximum power point tracking, wind speed forecasting, and wind turbine dynamics into account, and achieves a balance between power output maximization and operating cost minimization to further improve the overall efficiency of wind power generation. Specifically, through the proposed modeling and control methods, the wind power control problem is developed as a min-max optimal problem and efficiently solved with semi-definite programming. For the uncertain communication delay and communication loss (i.e. data loss) in WAMSs, the corresponding solutions are presented. First, the real-world communication delay is measured and analyzed, and the bounded modeling method for the communication delay is proposed for widearea applications and further applied for system-area and substation-area protection applications, respectively. The proposed bounded modeling method is expected to be an important tool in the planning, design, and operation of time-critical wide-area applications. Second, the real synchronization signal loss and synchrophasor data loss events are measured and analyzed. For the synchronization signal loss, the potential reasons and solutions are explored. For the synchrophasor data loss, a set of estimation methods are presented, including substitution, interpolation, and forecasting. The estimation methods aim to improve the accuracy and availability of WAMSs, and mitigate the effect of communication failure and data loss on wide-area applications

HopliteBuf FPGA Network-on-Chip: Architecture and Analysis

We can prove occupancy bounds of stall-free FIFOs used in deflection-free, low-cost, and high-speed FPGA overlay Network-on-chips (NoCs). In our work, we build on top of the HopliteRT livelock-free overlay NoC with an FPGA-friendly 2D unidirectional torus topology to propose the novel HopliteBuf NoC. In our new NoC, we strategically introduce stall-free FIFOs in the network and support these FIFOs with static analysis based on network calculus to compute FIFO occupancy, latency, and bandwidth bounds. The microarchitecture of HopliteBuf combines the performance benefits of conventional buffered NoCs (high throughput, low latency) with the cost advantages of deflection-routed NoCs (low FPGA area, high clock frequencies). Specifically, we look at two design variants of the HopliteBuf NoC: (1) Single corner-turn FIFO (W to S), and (2) Dual corner-turn FIFO (W to S+N). The single corner-turn (W to S) design is simpler and only introduces a buffering requirement for packets changing dimension from X ring to the downhill Y ring (or West to South). The dual corner-turn variant requires two FIFOs for turning packets going downhill (W to S) as well as uphill (W to N). The dual corner-turn design overcomes the mathematical analysis challenges associated with single corner-turn designs for communication workloads with cyclic dependencies between flow traversal paths at the expense of small increase in resource cost. Essentially, we resolve an analysis challenge with extra hardware resources. Across a range of 100 synthetically-generated workloads on a 5 x 5 NoC, HopliteBuf outperforms HopliteRT by 1.2-2x in terms of latency, 10% in terms of injection rate, and 30-60% in terms of flowset feasibiliy. These advantages come at the cost of 3-4x higher FPGA resource requirement for buffers and muxes. Our analysis also deliver latency bounds that are not only better than HopliteRT in absolute terms but also tighter by 2-3x allowing us to provision less hardware to meet our specifications

Enhanced Worst-case Timing Analysis of Ring-based Networks with Cyclic Dependencies using Network Calculus

The recent research effort towards defining new communication solutions for cyber-physical systems (CPS), to guarantee high availability level with limited cabling costs and complexity, has renewed the interest in ring-based networks. This topology has been recently used for various networked cyber-physical systems (Net-CPS), e.g., avionics and automotive, with the implementation of many Real Time Ethernet (RTE) profiles. A relevant issue for such networks is to prove timing predictability, a key requirement for safety-critical systems. For the most common ring-based Real Time Ethernet (RTE) profiles, conducting such performance analyses has been greatly simplified due to their implemented time-triggered communication scheme, e.g. Master/slave or TDMA. Unlike these existing approaches, we are interested in this paper in event-triggered ring-based networks, which guarantee high resource utilization efficiency and (re)confi\-gura\-tion flexibility, at the cost of increasing the timing analysis complexity. The implementation of such a communication scheme on top of a ring topology actually induces cyclic dependencies, in comparison to time-triggered solutions. To cope with this arising issue of cyclic dependencies, only few techniques have been proposed in the literature, mainly based on Network Calculus framework, and consist in analyzing locally the delay upper bound in each crossed node, resulting in pessimistic end-to-end delay bounds. Hence, the main contribution in this paper is enhancing the delay bounds tightness of such networks, through an innovative global analysis based on Network Calculus, considering the flow serialization phenomena along the flow path. An extensive analysis of such a proposal is conducted herein regarding the accuracy of delay bounds and its impact on the system performance, i.e., scalability and resource-efficiency; and the results highlight its outperformance, in comparison to conventional methods