Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

Design of the 12-bit Delta-Sigma Modulator using SC Technique for Vibration Sensor Output Processing

The work deals with the design of the 12-bit Delta-Sigma modulator using switched capacitors (SC) technique. The modulator serves to vibration sensor output processing. The first part describes the Delta-Sigma modulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the Delta-Sigma modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 um CMOS technology was used for design. Then, the Delta-Sigma modulator nonidealities were simulated and implemented into the MATLAB ideal model of the modulator. The model of real Delta-Sigma modulator was derived. Consequently, modulator coefficients were optimized. Finally, the corner analysis of the Delta-Sigma modulator with the optimized coefficients was simulated. The value of SNDR = 82.2 dB (ENOB = 13.4 bits) was achieved

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

STUDY OF FULLY-INTEGRATED LOW-DROPOUT REGULATORS

Department of Electrical EngineeringThis thesis focuses on the introduction of fully-integrated low-dropout regulators (LDOs). Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. LDOs get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. Digital loads such as DRAM and CPU need fast transient response, a wide range of load current providable LDOs. As an example, we present the design procedure of a fully-integrated LDO that obtains the desired PSRR. In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In digital LDOs, the techniques to improve transient response are introduced. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully-integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type. The future work is extracted from the considerations and limitations of conventional techniques.clos

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB

A comprehensive comparison between design for testability techniques for total dose testing of flash-based FPGAs

Radiation sources exist in different kinds of environments where electronic devices often operate. Correct device operation is usually affected negatively by radiation. The radiation resultant effect manifests in several forms depending on the operating environment of the device like total ionizing dose effect (TID), or single event effects (SEEs) such as single event upset (SEU), single event gate rupture (SEGR), and single event latch up (SEL). CMOS circuits and Floating gate MOS circuits suffer from an increase in the delay and the leakage current due to TID effect. This may damage the proper operation of the integrated circuit. Exhaustive testing is needed for devices operating in harsh conditions like space and military applications to ensure correct operations in the worst circumstances. The use of worst case test vectors (WCTVs) for testing is strongly recommended by MIL-STD-883, method 1019, which is the standard describing the procedure for testing electronic devices under radiation. However, the difficulty of generating these test vectors hinders their use in radiation testing. Testing digital circuits in the industry is usually done nowadays using design for testability (DFT) techniques as they are very mature and can be relied on. DFT techniques include, but not limited to, ad-hoc technique, built-in self test (BIST), muxed D scan, clocked scan and enhanced scan. DFT is usually used with automatic test patterns generation (ATPG) software to generate test vectors to test application specific integrated circuits (ASICs), especially with sequential circuits, against faults like stuck at faults and path delay faults. Despite all these recommendations for DFT, radiation testing has not benefited from this reliable technology yet. Also, with the big variation in the DFT techniques, choosing the right technique is the bottleneck to achieve the best results for TID testing. In this thesis, a comprehensive comparison between different DFT techniques for TID testing of flash-based FPGAs is made to help designers choose the best suitable DFT technique depending on their application. The comparison includes muxed D scan technique, clocked scan technique and enhanced scan technique. The comparison is done using ISCAS-89 benchmarks circuits. Points of comparisons include FPGA resources utilization, difficulty of designs bring-up, added delay by DFT logic and robust testable paths in each technique

Time-based low dropout regulator

The low dropout regulator (LDO) is an essential building block for modern integrated circuits. Traditional analog design faces formidable challenges as technology scales down, such as lower supply voltage and channel length modulation. Digital LDOs do not have the problems that analog LDOs have, but they usually have worse performance metrics. Therefore, a time-based LDO is proposed to combine the merits of both analog and digital together. In the end, the LDO achieves 0.6-1 V supply voltage range and 0.5-0.9 V output voltage range. The maximum output current is 50 mA and the worst case transient time is 1.58 μs under 0.6 V supply voltage. The maximum current efficiency is 99.98%