What are Memristor, Memcapacitor, and Meminductor?

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First order devices, hybrid memristors, and the frontiers of nonlinear circuit theory

Several devices exhibiting memory effects have shown up in nonlinear circuit theory in recent years. Among others, these circuit elements include Chua's memristors, as well as memcapacitors and meminductors. These and other related devices seem to be beyond the, say, classical scope of circuit theory, which is formulated in terms of resistors, capacitors, inductors, and voltage and current sources. We explore in this paper the potential extent of nonlinear circuit theory by classifying such mem-devices in terms of the variables involved in their constitutive relations and the notions of the differential- and the state-order of a device. Within this framework, the frontier of first order circuit theory is defined by so-called hybrid memristors, which are proposed here to accommodate a characteristic relating all four fundamental circuit variables. Devices with differential order two and mem-systems are discussed in less detail. We allow for fully nonlinear characteristics in all circuit elements, arriving at a rather exhaustive taxonomy of C^1-devices. Additionally, we extend the notion of a topologically degenerate configuration to circuits with memcapacitors, meminductors and all types of memristors, and characterize the differential-algebraic index of nodal models of such circuits.Comment: Published in 2013. Journal reference included as a footnote in the first pag

The Fourth Element: Characteristics, Modelling, and Electromagnetic Theory of the Memristor

In 2008, researchers at HP Labs published a paper in {\it Nature} reporting the realisation of a new basic circuit element that completes the missing link between charge and flux-linkage, which was postulated by Leon Chua in 1971. The HP memristor is based on a nanometer scale TiO$_2$ thin-film, containing a doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and nonvolatile RAM (NVRAM), they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for Integrated Circuits (ICs). This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell's equations. We also review Chua's arguments based on electromagnetic theory.Comment: 28 pages, 14 figures, Accepted as a regular paper - the Proceedings of Royal Society

OTA Based Mem-capacitor Validation and Implementation Using Commercially Available IC

This paper discusses a mem-capacitor circuit which is based on two MO-OTA along with a multiplier and 4 passive elements. This circuit is a charge-controlled memcapacitor emulator which is independent of any memristor also it consists the feature of electronic tunability. Additionally, this circuit is simpler and uses less hardware because it lacks a mutator and uses fewer active-passive components. The circuit behaviour is justified through various simulations in cadence Orcad tool with 180nm CMOS TSMC parameters. Additionally, conclusions from simulations and theory are validated experimentally through commercially available IC

Reliable SPICE Simulations of Memristors, Memcapacitors and Meminductors

Memory circuit elements, namely memristive, memcapacitive and meminductive systems, are gaining considerable attention due to their ubiquity and use in diverse areas of science and technology. Their modeling within the most widely used environment, SPICE, is thus critical to make substantial progress in the design and analysis of complex circuits. Here, we present a collection of models of different memory circuit elements and provide a methodology for their accurate and reliable modeling in the SPICE environment. We also provide codes of these models written in the most popular SPICE versions (PSpice, LTspice, HSPICE) for the benefit of the reader. We expect this to be of great value to the growing community of scientists interested in the wide range of applications of memory circuit elements

Solid-state memcapacitive system with negative and diverging capacitance

We suggest a possible realization of a solid-state memory capacitive (memcapacitive) system. Our approach relies on the slow polarization rate of a medium between plates of a regular capacitor. To achieve this goal, we consider a multi-layer structure embedded in a capacitor. The multi-layer structure is formed by metallic layers separated by an insulator so that non-linear electronic transport (tunneling) between the layers can occur. The suggested memcapacitor shows hysteretic charge-voltage and capacitance-voltage curves, and both negative and diverging capacitance within certain ranges of the field. This proposal can be easily realized experimentally, and indicates the possibility of information storage in memcapacitive devices

Ideal memcapacitors and meminductors are overunity devices

It is rigorously proved that ideal memcapacitors and meminductors are not passive or lossless devices, nor are they satisfying the weaker notion of cyclo-passivity, which arises when dropping the requirement of non-negativity of the storage function. Equivalently, this implies that there exist excitation profiles that allow to extract more energy from the device than it is supplied with; so that their energy conversion efficiency exceeds 100%. This means that ideal memcapacitors and meminductors constitute so-called overunity systems. An illustrative mechanical analogue is provided that explicitly confirms this property. Hence, the question arises if ideal memcapacitors and meminductors will just remain some mathematical toys or artefacts.Comment: 4 figure

Neuromorphic, Digital and Quantum Computation with Memory Circuit Elements

Memory effects are ubiquitous in nature and the class of memory circuit elements - which includes memristors, memcapacitors and meminductors - shows great potential to understand and simulate the associated fundamental physical processes. Here, we show that such elements can also be used in electronic schemes mimicking biologically-inspired computer architectures, performing digital logic and arithmetic operations, and can expand the capabilities of certain quantum computation schemes. In particular, we will discuss few examples where the concept of memory elements is relevant to the realization of associative memory in neuronal circuits, spike-timing-dependent plasticity of synapses, digital and field-programmable quantum computing

Cellular Nonlinear Networks: optimized implementation on FPGA and applications to robotics

L'objectiu principal d'aquesta tesi consisteix a estudiar la factibilitat d'implementar un sensor càmera CNN amb plena funcionalitat basat en FPGA de baix cost adequat per a aplicacions en robots mòbils. L'estudi dels fonaments de les xarxes cel•lulars no lineals (CNNs) i la seva aplicació eficaç en matrius de portes programables (FPGAs) s'ha complementat, d'una banda amb el paral•lelisme que s'estableix entre arquitectura multi-nucli de les CNNs i els eixams de robots mòbils, i per l'altre banda amb la correlació dinàmica de CNNs i arquitectures memristive. A més, els memristors es consideren els substituts dels futurs dispositius de memòria flash per la seva capacitat d'integració d'alta densitat i el seu consum d'energia prop de zero. En el nostre cas, hem estat interessats en el desenvolupament d’FPGAs que han deixat de ser simples dispositius per a la creació ràpida de prototips ASIC per esdevenir complets dispositius reconfigurables amb integració de la memòria i els elements de processament general. En particular, s'han explorat com les arquitectures implementades CNN en FPGAs poden ser optimitzades en termes d’àrea ocupada en el dispositiu i el seu consum de potència. El nostre objectiu final ens ah portat a implementar de manera eficient una CNN-UM amb complet funcionament a un baix cost i baix consum sobre una FPGA amb tecnología flash. Per tant, futurs estudis sobre l’arquitectura eficient de la CNN sobre la FPGA i la interconnexió amb els robots comercials disponibles és un dels objectius d'aquesta tesi que se seguiran en les línies de futur exposades en aquest treball.El objetivo principal de esta tesis consiste en estudiar la factibilidad de implementar un sensor cámara CNN con plena funcionalidad basado en FPGA de bajo coste adecuado para aplicaciones en robots móviles. El estudio de los fundamentos de las redes celulares no lineales (CNNs) y su aplicación eficaz en matrices de puertas programables (FPGAs) se ha complementado, por un lado con el paralelismo que se establece entre arquitectura multi -núcleo de las CNNs y los enjambres de robots móviles, y por el otro lado con la correlación dinámica de CNNs y arquitecturas memristive. Además, los memristors se consideran los sustitutos de los futuros dispositivos de memoria flash por su capacidad de integración de alta densidad y su consumo de energía cerca de cero. En nuestro caso, hemos estado interesados en el desarrollo de FPGAs que han dejado de ser simples dispositivos para la creación rápida de prototipos ASIC para convertirse en completos dispositivos reconfigurables con integración de la memoria y los elementos de procesamiento general. En particular, se han explorado como las arquitecturas implementadas CNN en FPGAs pueden ser optimizadas en términos de área ocupada en el dispositivo y su consumo de potencia. Nuestro objetivo final nos ah llevado a implementar de manera eficiente una CNN-UM con completo funcionamiento a un bajo coste y bajo consumo sobre una FPGA con tecnología flash. Por lo tanto, futuros estudios sobre la arquitectura eficiente de la CNN sobre la FPGA y la interconexión con los robots comerciales disponibles es uno de los objetivos de esta tesis que se seguirán en las líneas de futuro expuestas en este trabajo.The main goal of this thesis consists in studying the feasibility to implement a full-functionality CNN camera sensor based on low-cost FPGA device suitable for mobile robotic applications. The study of Cellular Nonlinear Networks (CNNs) fundamentals and its efficient implementation on Field Programmable Gate Arrays (FPGAs) has been complemented, on one side with the parallelism established between multi-core CNN architecture and swarm of mobile robots, and on the other side with the dynamics correlation of CNNs and memristive architectures. Furthermore, memristors are considered the future substitutes of flash memory devices because of its capability of high density integration and its close to zero power consumption. In our case, we have been interested in the development of FPGAs that have ceased to be simple devices for ASIC fast prototyping to become complete reconfigurable devices embedding memory and processing elements. In particular, we have explored how the CNN architectures implemented on FPGAs can be optimized in terms of area occupied on the device or power consumption. Our final accomplishment has been implementing efficiently a fully functional reconfigurable CNN-UM on a low-cost low-power FPGA based on flash technology. Therefore, further studies on an efficient CNN architecture on FPGA and interfacing it with commercially-available robots is one of the objectives of this thesis that will be followed in the future directions exposed in this work