Reliability Analysis of Hafnium Oxide Dielectric Based Nanoelectronics

With the physical dimensions ever scaling down, the increasing level of sophistication in nano-electronics requires a comprehensive and multidisciplinary reliability investigation. A kind of nano-devices, HfO2-based high-k dielectric films, are studied in the statistical aspect of reliability as well as electrical and physical aspects of reliability characterization, including charge trapping and degradation mechanisms, breakdown modes and bathtub failure rate estimation. This research characterizes charge trapping and investigates degradation mechanisms in high-k dielectrics. Positive charges trapped in both bulk and interface contribute to the interface state generation and flat band voltage shift when electrons are injected from the gate under a negative gate bias condition.A negligible number of defects are generated until the stress voltage increases to a certain level. As results of hot electrons and positive charges trapped in the interface region, the difference in the breakdown sequence is attributed to the physical thickness of the bulk high-k layer and the structure of the interface layer. Time-to-breakdown data collected in the accelerated life tests are modeled with a bathtub failure rate curve by a 3-step Bayesian approach. Rather than individually considering each stress level in accelerating life tests (ALT), this approach derives the change point and the priors for Bayesian analysis from the time-to-failure data under neighborhood stresses, based on the relationship between the lifetime and stress voltage. This method can provide a fast and reliable estimation of failure rate for burn-in optimization when only a small sample of data is available

EXPERIMENTAL STUDY OF BIAS TEMPERATURE INSTABILITY AND PROGRESSIVE BREAKDOWN OF ADVANCED GATE DIELECTRICS

With shrinking gate dielectrics, the reliability requirements of semiconductor gate dielectrics become more and more difficult to maintain. New physical mechanisms and phenomena are discovered and new challenges arise. At the same time, some issues, which have been minor in the past, begin to show bigger impact, such as the Negative Bias Temperature Instability issue. The dynamic NBTI phenomenon was studied with ultrathin SiO2 and HfO2 devices. With a dynamic stress condition, the device lifetime can be largely extended due to the reduced NBTI degradation. This reduction is contributed to the annealing of fixed oxide charges during the stress off period. A mathematical model is also established to explain this phenomenon. With alternative gate dielectrics' introduction, new issues associated with these materials and device structures are also raised. Those issues need to be studied in detail before fully incorporation of new materials. Compared with SiO2 devices, the NBTI degradation of HfO2 has a similar trend. However, it is found that they have different frequency response than the SiO2 devices. This difference is later found due to the traps inside the gate dielectrics. Detailed studies show that NBTI degradations at dc stress and dynamic stress conditions have different temperature acceleration factors due to the bulk traps. The disappearance of this difference by insetting a detrapping period further proves this observation. As we enter the ultrathin gate dielectrics regime, the electron tunneling mechanisms behind the gate dielectrics breakdown shift. Consequently, gate dielectrics breakdown mode also shifts from the clear-detected hard breakdown to the noisy soft breakdown. Thus new lifetime extrapolation models are needed. The progressive breakdown of ultrathin SiO2 is studied by a two-step test methodology. By monitoring the degradation of the progressive breakdown path in terms of the activation energy, the voltage acceleration factor, two kinds of breakdown filaments, the stable one and the unstable one, were studied. The stable filament is found to be a breakdown filament independent of the original breakdown filament, and the unstable filament is the continuing degradation of the original filament

Reliability modeling of ultra-thin gate oxide and high-k dielectrics for nano-scale CMOS devices

Ph.DDOCTOR OF PHILOSOPH

Recent Advances in Metal, Ceramic, and Metal-Ceramic Composite Films/Coatings

This reprint gathers works on various coating materials and technologies aimed at the improvement of materials’ properties, such as corrosion resistance or biocompatibility. Systematic studies demonstrate how the structure and morphology of coatings can change the mechanical, chemical and various functional properties of materials. The reprint contributes to the better understanding of various phenomena induced by metal, ceramic or composite coatings in core materials and, thus, it can help in the more rational design of the selected material’s properties in future studies by the application of coatings

Analysis of breakdown in ferromagnetic tunnel junctions

Due to their very thin tunnel barrier layer, magnetic tunnel junctions show dielectric breakdown at voltages of the order of 1 V. At the moment of breakdown, a highly conductive short is formed in the barrier and is visible as a hot spot. The breakdown effect is investigated by means of voltage ramp experiments on a series of nominally identical Co/Al2O3/Co tunnel junctions. The results are described in terms of a voltage dependent breakdown probability, and are further analyzed within the framework of a general model for the breakdown probability in dielectric materials, within which it is assumed that at any time the breakdown probability is independent of the (possibly time-dependent) voltage that has been previously applied. The experimental data can be described by several specific forms of the voltage breakdown probability function. A comparison with the models commonly used for describing thin film SiO2 breakdown is given, as well as suggestions for future experiments

TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology

In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies. In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature. In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides. In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide. In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed. An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks

A New Generation of Smart Multifunctional Additive for High-Temperature Lubrication in Metal Forming Processes

High-temperature lubrication plays a critical role in various engineering processes of hot metal forming (e.g. hot forging, hot rolling, hot extrusion…). It has been acknowledged that high energy efficiency, low material losses, and optimum product quality can be achieved by the application of effective lubricants. Although sodium-containing glass melts have proven themselves as the outstanding candidate lubricant for hot metalworking processes, they have reached their performance limit. In addition, the concern about the corrosion of sodium toward oxide scale is also highlighted. The current study not only puts an effort into improving the lubricity of the existing melt lubricants but also concentrates on the formulation of the lubricant package for high-temperature manufacturing processes. Particularly, the development of the novel multifunctional lubricant additives from the existing solid lubricants is at the heart of the research activities