Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Reliability Study Of Ingap/gaas Heterojunction Bipolar Transistor Mmic Technology By Characterization, Modeling And Simulation

Recent years have shown real advances of microwave monolithic integrated circuits (MMICs) for millimeter-wave frequency systems, such as wireless communication, advanced imaging, remote sensing and automotive radar systems, as MMICs can provide the size, weight and performance required for these systems. Traditionally, GaAs pseudomorphic high electron mobility transistor (pHEMT) or InP based MMIC technology has dominated in millimeter-wave frequency applications because of their high fT and fmax as well as their superior noise performance. But these technologies are very expensive. Thus, for low cost and high performance applications, InGaP/GaAs heterojunction bipolar transistors (HBTs) are quickly becoming the preferred technology to be used due to their inherently excellent characteristics. These features, together with the need for only one power supply to bias the device, make InGaP/GaAs HBTs very attractive for the design of high performance fully integrated MMICs. With the smaller dimensions for improving speed and functionality of InGaP/GaAs HBTs, which dissipate large amount of power and result in heat flux accumulated in the device junction, technology reliability issues are the first concern for the commercialization. As the thermally triggered instabilities often seen in InGaP/GaAs HBTs, a carefully derived technique to define the stress conditions of accelerated life test has been employed in our study to acquire post-stress device characteristics for the projection of long-term device performance degradation pattern. To identify the possible origins of the post-stress device behaviors observed experimentally, a two iv dimensional (2-D) TCAD numerical device simulation has been carried out. Using this approach, it is suggested that the acceptor-type trapping states located in the emitter bulk are responsible for the commonly seen post-stress base current instability over the moderate base-emitter voltage region. HBT-based MMIC performance is very sensitive to the variation of core device characteristics and the reliability issues put the limit on its radio frequency (RF) behaviors. While many researchers have reported the observed stress-induced degradations of GaAs HBT characteristics, there has been little published data on the full understanding of stress impact on the GaAs HBTbased MMICs. If care is not taken to understand this issue, stress-induced degradation paths can lead to built-in circuit failure during regular operations. However, detection of this failure may be difficult due to the circuit complexity and lead to erroneous data or output conditions. Thus, a practical and analytical methodology has been developed to predict the stress impacts on HBTbased MMICs. It provides a quick way and guidance for the RF design engineer to evaluate the circuit performance with reliability considerations. Using the present existing EDA tools (Cadance SpectreRF and Agilent ADS) with the extracted pre- and post-stress transistor models, the electrothermal stress effects on InGaP/GaAs HBT-based RF building blocks including power amplifier (PA), low-noise amplifier (LNA) and oscillator have been systematically evaluated. This provides a potential way for the RF/microwave industry to save tens of millions of dollars annually in testing costs. v The world now stands at the threshold of the age of advanced GaAs HBT MMIC technology and researchers have been exploring here for years. The reliability of GaAs HBT technology is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation provide methods and guidance for the RF designers to achieve more reliable RF circuits with advanced GaAs HBT technology in the future

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%

Caractérisation et modélisation de la fiabilité des transistors et circuits millimétriques conçus en technologies BiCMOS et CMOS

De nos jours, l'industrie de la microélectronique développe des nouvelles technologies qui permettent l'obtention d'applications du quotidien alliant rapidité, basse consommation et hautes performances. Pour cela, le transistor, composant actif élémentaire et indispensable de l'électronique, voit ses dimensions miniaturisées à un rythme effréné suivant la loi de Moore de 1965. Cette réduction de dimensions permet l'implémentation de plusieurs milliards de transistors sur des surfaces de quelques millimètres carrés augmentant ainsi la densité d'intégration. Ceci conduit à une production à des coûts de fabrication constants et offre des possibilités d'achats de produits performants à un grand nombre de consommateurs. Le MOSFET (Metal Oxide Semiconductor Field Effect Transistor), transistor à effet de champ, aussi appelé MOS, représente le transistor le plus utilisé dans les différents circuits issus des industries de la microélectronique. Ce transistor possède des longueurs électriques de 14 nm pour les technologies industrialisables les plus avancées et permet une densité intégration maximale spécialement pour les circuits numériques tels que les microprocesseurs. Le transistor bipolaire, dédié aux applications analogiques, fut inventé avant le transistor MOS. Cependant, son développement correspond à des noeuds technologiques de génération inférieure par rapport à celle des transistors MOS. En effet, les dimensions caractéristiques des noeuds technologiques les plus avancés pour les technologies BiCMOS sont de 55 nm. Ce type de transistor permet la mise en oeuvre de circuits nécessitant de très hautes fréquences d'opération, principalement dans le secteur des télécommunications, tels que les radars anticollisions automobiles fonctionnant à 77 GHz. Chacun de ces types de transistors possède ses propres avantages et inconvénients. Les avantages du transistor MOS reposent principalement en deux points qui sont sa capacité d'intégration et sa faible consommation lorsqu'il est utilisé pour réaliser des circuits logiques. Sachant que ces deux types de transistors sont, de nos jours, comparables du point de vue miniaturisation, les avantages offerts par le transistor bipolaire diffèrent de ceux du transistor MOS. En effet, le transistor bipolaire supporte des niveaux de courants plus élevés que celui d'un transistor MOS ce qui lui confère une meilleure capacité d'amplification de puissance. De plus, le transistor bipolaire possède une meilleure tenue en tension et surtout possède des niveaux de bruit électronique beaucoup plus faibles que ceux des transistors MOS. Ces différences notables entre les deux types de transistors guideront le choix des concepteurs suivant les spécifications des clients. L'étude qui suit concerne la fiabilité de ces deux types de transistors ainsi que celle de circuits pour les applications radio fréquences (RF) et aux longueurs d'ondes millimétriques (mmW) pour lesquels ils sont destinés. Il existe dans la littérature de nombreuses études de la fiabilité des transistors MOS. Concernant les transistors bipolaires peu d'études ont été réalisées. De plus peu d'études ont été menées sur l'impact de la fiabilité des transistors sur les circuits. L'objectif de ce travail est d'étudier le comportement de ces deux types de transistors mais aussi de les replacer dans le contexte de l'utilisateur en étudiant la fiabilité de quelques circuits parmi les plus usités dans les domaines hyperfréquence et millimétrique. Nous avons aussi essayé de montrer qu'il était possible de faire évoluer les règles de conception actuellement utilisées par les concepteurs tout en maintenant la fiabilité attendue par les clients.Nowadays, the microelectronics industry develops new technologies that allow the production of applications combining high speed, low power consumption and high performance. For this, the transistor, active elementary and essential component of electronics, sees its miniaturized dimensions at a breakneck pace following Moore's Law in 1965. This size reduction allows the implementation of several billion transistors on surfaces of a few square millimeters and increasing the integration density. This leads to a production at constant costs and offers opportunities for shopping performing products at a large number of consumers. The MOSFET (Metal Oxide Semiconductor Field Effect Transistor), field effect transistor, also called MOS transistor is the most used in different circuits coming from the microelectronics industries. This transistor has electrical lengths of 14 nm for the industrially most advanced technology and allows a maximum integration density specifically for digital circuits such as microprocessors. Bipolar transistor, dedicated to analog applications, was invented before the MOS transistor. However, the characteristic dimensions of the most advanced technologies for BiCMOS technology nodes is 55 nm. This type of transistor enables the implementation of systems requiring very high frequency operation, mainly in the telecommunications industry , such as automotive collision avoidance radar operating at 77 GHz. Each of these transistors has its own advantages and disadvantages. The advantages of MOS transistor are mainly based on two points that are its integration capacity and its low power consumption when used to implement logic circuits. Knowing that these two types of transistors are, nowadays, comparable on the miniaturization aspect, benefits of bipolar transistor differ from those of the MOS transistor. Indeed, the bipolar transistor supports higher current levels than a MOS transistor which gives it a greater ability of power amplification. Moreover , the bipolar transistor has an improved breakdown voltage and especially features electronic noise levels much lower than those of the MOS transistors. These significant differences between the two transistors types will guide the designers choice according to the customer specifications. The following study relates the reliability of these two transistors types as well as circuits for radio frequency (RF) applications and millimeter wavelengths (mmW) for which they are intended. There are in the literature many studies of the reliability of MOS transistors. Regarding bipolar transistors few studies have been conducted. In addition few studies have been conducted on the impact of the reliability of transistors on circuits. The objective of this work is to study the behavior of these two types of transistors but also to place them in the user context by studying the reliability of some of most used circuits in the microwave and millimeter fields. We also tried to show that it was possible to change the design rules currently used by designers while maintaining the expected reliability by the counsumers.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Design and development of a CMOS power amplifier for digital applications

Master'sMASTER OF ENGINEERIN

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law

Using SiGe HBTs for quantum science at deep cryogenic temperatures

The objective of this research is to investigate the feasibility of using BiCMOS technology for these quantum science applications and clear some major roadblocks. The requirement for these applications is detailed, and the research is conducted in a systematic way targeting four important aspects of SiGe HBTs, namely, cryogenic characterizations, device physics, compact modeling, and circuit designs.Ph.D

Strained Si heterojunction bioploar transistors

This dissertation addresses the world’s first demonstration of strained Si Heterojunction Bipolar Transistors (sSi HBTs). The conventional SiGe Heterojunction Bipolar Transistor (SiGe HBT), which was introduced as a commercial product in 1999 (after its first demonstration in 1988), has become an established device for high-speed applications. This is due to its excellent RF performance and compatibility with CMOS processing. It has enabled silicon-based technology to penetrate the rapidly growing market for wide bandwidth and wireless telecommunications once reserved for more expensive III–V technologies. SiGe HBTs is realised by the pseudomorphic growth of SiGe on a Si substrate, which allows engineering of the base region to improve performance. In this way the base has a smaller energy band gap than the emitter, which increases the gain. The energy band gap of SiGe reduces with increasing Ge composition, but the maximum Ge composition is limited by the amount of strain that can be accommodated within a given base layer thickness. Therefore, a new innovation is necessary to overcome this limitation and meet the continuous demand for high speed devices. Growing the SiGe base layer over a relaxed SiGe layer (Strain Relaxed Buffer) can increase the amount of Ge that can be incorporated in the base, hence, increasing the device performance. In this thesis, experimental data is presented to demonstrate the realisation of sSi HBTs. The performance of this novel device has been also investigated and explained using TCAD tool.EThOS - Electronic Theses Online ServiceEngineering and Physical Sciences Research CouncilGBUnited Kingdo

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H