Voltage Divider Effect for the Improvement of Variability and Endurance of TaOx Memristor

The impact of a series resistor (RS) on the variability and endurance performance of memristor was studied in the TaOx memristive system. A dynamic voltage divider between the RS and memristor during both the set and the reset switching cycles can suppress the inherent irregularity of the voltage dropped on the memristor, resulting in a greatly reduced switching variability. By selecting the proper resistance value of RS for the set and reset cycles respectively, we observed a dramatically improved endurance of the TaOx memristor. Such a voltage divider effect can thus be critical for the memristor applications that require low variability, high endurance and fast speed

Low-Cost Test and Characterization Platform for Memristors

The electrical Testing and Characterization of the devices built under research conditions on silicon wafers, diced wafers, or package parts have hampered research since the beginning of integrated circuits. The challenges of performing electrical characterization on devices are to acquire useful and accurate data, the ease of use of the test platform, the portability of the test equipment, the ability to automate quickly, to allow modifications to the platform, the ability to change the configuration of the Device Under Test (DUT) or the Memristor Based Design (MBD), and to do this within budget. The devices that this research is focused on are memristors with unique test challenges. Some of the tests performed on memristors are Voltage sweeps, pulsing of Voltages, and threshold Voltages. Standard methods of testing memristors usually require hands-on experience, multiple bulky work stations, and hours of training. This work reports a novel, low-cost, portable test and characterization platform for many types of memristors with a voltage range from -10V to +10V, which is portable, low-cost, built with off-the-shelf components, and with configurability through software and hardware. To demonstrate the performance of the platform, the platform was able to take a virgin memristor from “forming” to operation voltages, and then incrementally change resistances by Voltage Pulsing. The platform within this work allows the researcher flexibility in electrical characterization by being able to accept many memristor types and MBDs, and applying environmental conditions to the MBD, with this flexibility of the platform the productivity of the researcher will increase

Memristors: a short review on fundamentals, structures, materials and applications

The paper contains a short literature review on the subject of special type of thin film structures with resistive-switching memory effect. In the literature, such structures are commonly labeled as "memristors". The word "memristor" originates from two words: "memory" and "resistor". For the first time, the memristor was theoretically described in 1971 by Leon Chua as the 4th fundamental passive electronics element with a non-linear current-voltage behavior. The reported area of potential usage of memristor is enormous. It is predicted that the memristor could find application, for example in the domain of nonvolatile random access memory, flash memory, neuromorphic systems and so forth. However, in spite of the fact that plenty of papers have been published in the subject literature to date, the memristor still behaves as a "mysterious" electronic element. It seems that, one of the important reasons that such structures are not yet in practical use, is unsufficient knowledge of physical phenomena determining occurrence of the switching effect. The present paper contains a literature review of available descriptions of theoretical basis of the memristor structures, used materials, structure configurations and discussion about future prospects and limitations

Memristors: a short review on fundamentals, structures, materials and applications

The paper contains a short literature review on the subject of special type of thin film structures with resistive-switching memory effect. In the literature, such structures are commonly labeled as "memristors". The word "memristor" originates from two words: "memory" and "resistor". For the first time, the memristor was theoretically described in 1971 by Leon Chua as the 4th fundamental passive electronics element with a non-linear current-voltage behavior. The reported area of potential usage of memristor is enormous. It is predicted that the memristor could find application, for example in the domain of nonvolatile random access memory, flash memory, neuromorphic systems and so forth. However, in spite of the fact that plenty of papers have been published in the subject literature to date, the memristor still behaves as a "mysterious" electronic element. It seems that, one of the important reasons that such structures are not yet in practical use, is unsufficient knowledge of physical phenomena determining occurrence of the switching effect. The present paper contains a literature review of available descriptions of theoretical basis of the memristor structures, used materials, structure configurations and discussion about future prospects and limitations

Dynamical memristive neural networks and associative self-learning architectures using biomimetic devices

While there is an abundance of research on neural networks that are “inspired” by the brain, few mimic the critical temporal compute features that allow the brain to efficiently perform complex computations. Even fewer methods emulate the heterogeneity of learning produced by biological neurons. Memory devices, such as memristors, are also investigated for their potential to implement neuronal functions in electronic hardware. However, memristors in computing architectures typically operate as non-volatile memories, either as storage or as the weights in a multiply-and-accumulate function that requires direct access to manipulate memristance via a costly learning algorithm. Hence, the integration of memristors into architectures as time-dependent computational units is studied, starting with the development of a compact and versatile mathematical model that is capable of emulating flux-linkage controlled analog (FLCA) memristors and their unique temporal characteristics. The proposed model, which is validated against experimental FLCA LixNbO2 intercalation devices, is used to create memristive circuits that mimic neuronal behavior such as desensitization, paired-pulse facilitation, and spike-timing-dependent plasticity. The model is used to demonstrate building blocks of biomimetic learning via dynamical memristive circuits that implement biomimetic learning rules in a self-training neural network, with dynamical memristive weights that are capable of associative lifelong learning. Successful training of the dynamical memristive neural network to perform image classification of handwritten digits is shown, including lifelong learning by having the dynamical memristive network relearn different characters in succession. An analog computing architecture that learns to associate input-to-input correlations is also introduced, with examples demonstrating image classification and pattern recognition without convolution. The biomimetic functions shown in this paper result from fully ion-driven memristive circuits devoid of integrating capacitors and thus are instructive for exploiting the immense potential of memristive technology for neuromorphic computation in hardware and allowing a common architecture to be applied to a wide range of learning rules, including STDP, magnitude, frequency, and pulse shape among others, to enable an inorganic implementation of the complex heterogeneity of biological neural systems

Bio-inspired Neuromorphic Computing Using Memristor Crossbar Networks

Bio-inspired neuromorphic computing systems built with emerging devices such as memristors have become an active research field. Experimental demonstrations at the network-level have suggested memristor-based neuromorphic systems as a promising candidate to overcome the von-Neumann bottleneck in future computing applications. As a hardware system that offers co-location of memory and data processing, memristor-based networks represent an efficient computing platform with minimal data transfer and high parallelism. Furthermore, active utilization of the dynamic processes during resistive switching in memristors can help realize more faithful emulation of biological device and network behaviors, with the potential to process dynamic temporal inputs efficiently. In this thesis, I present experimental demonstrations of neuromorphic systems using fabricated memristor arrays as well as network-level simulation results. Models of resistive switching behavior in two types of memristor devices, conventional first-order and recently proposed second-order memristor devices, will be first introduced. Secondly, experimental demonstration of K-means clustering through unsupervised learning in a memristor network will be presented. The memristor based hardware systems achieved high classification accuracy (93.3%) on the standard IRIS data set, suggesting practical networks can be built with optimized memristor devices. Thirdly, implementation of a partial differential equation (PDE) solver in memristor arrays will be discussed. This work expands the capability of memristor-based computing hardware from ‘soft’ to ‘hard’ computing tasks, which require very high precision and accurate solutions. In general first-order memristors are suitable to perform tasks that are based on vector-matrix multiplications, ranging from K-means clustering to PDE solvers. On the other hand, utilizing internal device dynamics in second-order memristors can allow natural emulation of biological behaviors and enable network functions such as temporal data processing. An effort to explore second-order memristor devices and their network behaviors will be discussed. Finally, we propose ideas to build large-size passive memristor crossbar arrays, including fabrication approaches, guidelines of device structure, and analysis of the parasitic effects in larger arrays.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147610/1/yjjeong_1.pd

A Memristor-Based Neuromorphic Computing Application

Artificial neural networks have recently received renewed interest because of the discovery of the memristor. The memristor is the fourth basic circuit element, hypothesized to exist by Leon Chua in 1971 and physically realized in 2008. The two-terminal device acts like a resistor with memory and is therefore of great interest for use as a synapse in hardware ANNs. Recent advances in memristor technology allowed these devices to migrate from the experimental stage to the application stage. This Master\u27s thesis presents the development of a threshold logic gate (TLG), which is a special case of an ANN, implemented with discrete circuit elements using memristors as synapses. Further, a programming circuit is developed, allowing the memristors and therefore the network to be reconfigured and trained in real-time. The results show that memristors are indeed viable for use in ANNs, but are somewhat hard to control as a lot of intrinsic device characteristics are still under investigation and are currently not fully understood. A simple threshold logic gate was built and can be reconfigured to implement AND, OR, NAND, and NOR functionality. The findings presented here contribute towards improvements on the device as well as algorithmic level to implement a memristor-based ANN capable of on-line learning

Hardware Considerations for Signal Processing Systems: A Step Toward the Unconventional.

As we progress into the future, signal processing algorithms are becoming more computationally intensive and power hungry while the desire for mobile products and low power devices is also increasing. An integrated ASIC solution is one of the primary ways chip developers can improve performance and add functionality while keeping the power budget low. This work discusses ASIC hardware for both conventional and unconventional signal processing systems, and how integration, error resilience, emerging devices, and new algorithms can be leveraged by signal processing systems to further improve performance and enable new applications. Specifically this work presents three case studies: 1) a conventional and highly parallel mix signal cross-correlator ASIC for a weather satellite performing real-time synthetic aperture imaging, 2) an unconventional native stochastic computing architecture enabled by memristors, and 3) two unconventional sparse neural network ASICs for feature extraction and object classification. As improvements from technology scaling alone slow down, and the demand for energy efficient mobile electronics increases, such optimization techniques at the device, circuit, and system level will become more critical to advance signal processing capabilities in the future.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116685/1/knagphil_1.pd

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed