On-chip electrochemical capacitors and piezoelectric energy harvesters for self-powering sensor nodes

On-chip sensing and communications in the Internet of things platform have benefited from the miniaturization of faster and low power complementary-metal-oxide semiconductor (CMOS) microelectronics. Micro-electromechanical systems technology (MEMS) and development of novel nanomaterials have further improved the performance of sensors and transducers while also demonstrating reduction in size and power consumption. Integration of such technologies can enable miniaturized nodes to be deployed to construct wireless sensor networks for autonomous data acquisition. Their longevity, however, is determined by the lifetime of the power supply. Traditional batteries cannot fully fulfill the demands of sensor nodes that require long operational duration. Thus, we require solutions that produce their own electricity from the surroundings and store them for future utility. Furthermore, manufacturing of such a power supply must be compatible with CMOS and MEMS technology. In this thesis, we will describe on-chip electrochemical capacitors and piezoelectric energy harvesters as components of such a self-powered sensor node. Our piezoelectric microcantilevers confirm the feasibility of fabricating micro electro-mechanical-systems (MEMS) size two-degree-of-freedom systems which can address the major issue of small bandwidth of piezoelectric micro-energy harvesters. These devices use a cut-out trapezoidal cantilever beam, limited by its footprint area i.e. a 1 cm$^2$ silicon die, to enhance the stress on the cantilever\u27s free end while reducing the gap remarkably between its first two eigenfrequencies in the 400 - 500 Hz and in the 1 - 2 kHz range. The energy from the M-shaped harvesters could be stored in rGO based on-chip electrochemical capacitors. The electrochemical capacitors are manufactured through CMOS compatible, reproducible, and reliable micromachining processes such as chemical vapor deposition of carbon nanofibers (CNF) and spin coating of graphene oxide based (GO) solutions. The impact of electrode geometry and electrode thickness is studied for CNF based electrodes. Furthermore, we have also demonstrated an improvement in their electrochemical performance and yield of spin coated electrochemical capacitors through surface roughening from iron and chromium nanoparticles. The CVD grown CNF and spin coated rGO based devices are evaluated for their respective trade-offs. Finally, to improve the energy density and demonstrate the versatility of the spin coating process, we manufactured electrochemical capacitors from various GO based composites with functional groups heptadecan-9-amine and octadecanamine. The materials were used as a stack to demonstrate high energy density for spin coated electrochemical capacitors. We have also examined the possibility of integrating these devices into a power management unit to fully realize a self-powering on-chip power supply through survey of package fabrication, choice of electrolyte, and device assembly

Investigation into Solder Joint Failure in Portable Electronics Subjected to Drop Impact

Ph.DDOCTOR OF PHILOSOPH

COMPARISON OF INTERCONNECT FAILURES OF ELECTRONIC COMPONENTS MOUNTED ON FR-4 BOARDS WITH SN37PB AND SN3.0AG0.5CU SOLDERS UNDER RAPID LOADING CONDITIONS.

Electronic circuit boards can experience rapid loading through shock or vibration events during their lives; these events can happen in transportation, manufacture, or in field conditions. Due to the lead-free migration, it is necessary to evaluate how this rapid loading affects the durability of a leading lead free solder alternative (Sn3.0Ag0.5Cu) assemblies as compared with traditional eutectic lead based solder Sn37Pb assemblies. A literature review showed that there is little agreement on the fatigue behavior of Sn37Pb solder assemblies and Sn3.0Ag0.5Cu solder assemblies subjected to rapid loading. To evaluate the failure behavior of Sn37Pb and Sn3.0Ag0.5Cu solder assemblies under rapid loading conditions, leadless chip resistors (LCR), ball grid arrays (BGA), small outline integrated circuits (SOIC), and small outline transistors (SOT) were subjected to four point bend tests via a servo-hydraulic testing machine at printed wiring board (PWB) strain rates greater than 0.1/s. The PWB strain was the metric used to evaluate the failures. The PBGAs and LCRs were examined with both Sn37Pb and Sn3.0Ag0.5Cu solders. There was no significant difference found in the resulting test data for the behavior of the two solder assembly types in the high cycle fatigue regime. PBGA assemblies with both solders were also evaluated at a higher strain rate, approximately 1/s, using drop testing. There was no discernable difference found between the assemblies as well as no difference in the failure rate of the PBGAs at this higher strain rate. The PWB strain was converted to an equivalent solder stress index using finite element analysis. This equivalent stress index value was used to compare the results from the LCR and BGA testing for Sn37Pb and Sn3.0Ag0.5Cu. Independently generated BGA data that differed with respect to many testing variables was adjusted and incorporated to this comparison. The resulting plot did not show any significant differences between the behaviors of the two solder assemblies under rapid loading outside of the ultra low cycle fatigue regime, where the assemblies with Sn37Pb solder outperformed the assemblies with SnAgCu solder

Rinnakkainen yhdistelmätestausmenetelmä elektronisten kokoonpanojen kokonaisvaltaisempaan ja tehokkaampaan luotettavuustestaukseen

Perinteisesti elektroniikan kokoonpanojen luotettavuutta on testattu kiihdytetyillä elinaikatesteillä yhtä rasitusparametriä hyväksikäyttäen. Tässä diplomityössä pyrittiin kehittämään uusi rinnakkainen yhdistelmätestausmenetelmä, joka simuloisi tuotteiden todellisia käyttöolosuhteita todenmukaisemmin. Rasituksien yhdistämisen uskotaan myös nopeuttavan vauriomekanismejä ja täten lyhentävän testaukseen käytettyä aikaa. Työ keskittyi termomekaanisten ja mekaanisten rasitusten yhdistämiseen. Työn kirjallisuusosa käsitteli kiihdytettyjä elinaikatestejä. Oleelliset yhden rasituksen testimenetelmät käytiin läpi ennen syventymistä useita rasitusparametrejä hyödyntäviin testeihin kirjallisuusselvityksen avulla. Työn kokeellisessa osassa yhdistettiin tehosyklaus ja tärinätestaus yhdeksi testimenetelmäksi. Ennen rasitusten yhdistämistä suoritettiin yhden rasitusparametrin tehosykli- ja tärinätestit varsinaisten testiparametrien määrittämiseksi ja rinnakkaistestauksen vikaantumismekanismien selvittämiseksi. Tulokset olivat yhtäpitäviä aikaisempien asiasta suoritettujen tutkimusten kanssa, elinaikojen yhdistelmätestauksessa ollessa huomattavasti lyhyempiä kuin oli oletettu erillisten yhden rasitusparametrin testien tulosten perusteella. Yhdistelmätestauksessa havaitut vikaantumismoodit olivat hyvin samankaltaisia tärinätesteissä havaittujen moodien kanssa ja vaurioitumisnopeuden kasvun oletettiin johtuvan juoteliitoksien lämpötilasta aiheutuvien mekaanisten ominaisuuksien muutoksista. Tulokset osoittivat, että testiparametrien huolellisella valinnalla voidaan uudella menetelmällä saavuttaa todellisia käyttöympäristöjä todenmukaisemmin edustava rasitusympäristö sekä lyhentää testiaikoja merkittävästi. On myös huomioitava, että yksittäin lähes merkityksettömillä rasituksilla saattaa olla merkittäviä yhteisvaikutuksia luotettavuuteen, joita ei voida huomioida perinteisillä yhden rasituksen testeillä.Traditionally the reliability and lifetime predictions of electronic assemblies have been conducted by employing single load accelerated life tests. This thesis aimed to develop a new concurrent reliability testing method that would offer a more realistic representation of actual use environments. Additionally, the combination of several loadings is expected to accelerate the damage accumulation, thus decreasing the associated testing times and costs. The focus was on the combination of thermomechanical and mechanical loads. Accelerated life tests were analyzed in the literature part. The relevant conventional accelerated life tests utilizing a single loading parameter were discussed before addressing multiple loading tests by giving a literature review on the current status of the subject. The experimental part combined power cycling and vibration loading into a single concurrent test method. To determine the actual test parameters and to clarify the failure modes and mechanisms in concurrent loading, single loading tests were conducted before the loads were combined. The experimental results were consistent with the previous results reported in literature with observed lifetimes considerably shorter than expected based on the single load test results. Observed failure modes in concurrent testing closely resembled those observed in pure mechanical loading, but the accelerated damage accumulation rate was attributed to the temperature related change of material properties. It was concluded that when the loading parameters are carefully set, significant improvements in both the lifelikeness of the loading conditions and in effectiveness can be achieved with the new test method. The results indicated that even under relatively small magnitude single loads the interactions of the various loadings can have significant effects on reliability that cannot be accounted for with single load tests

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems

Carbon Nanotube Based Interconnect Material for Electronic Applications

Carbon nanotubes (CNTs) are considered as a candidate material for future electronic interconnect applications. This thesis summarizes the research work on the fabrication and characterization of CNT-based interconnect systems, and explores the possibilities of integrating CNTs into various electronic interconnect scenarios. CNT material properties and fabrication methods are introduced as well as its potential for solving the future interconnect challenges. The technology development works are presented in detail in four categories: synthesis, densification, coating and transfer. The principles of the chemical vapor deposition (CVD) method for producing the CNTs are described and discussed. Densification methods are developed in order to increase the volume density of the pristine porous CVD-grown CNTs. Two techniques, vapor-based densification and paper-mediated wet densification, have been proposed and characterized. CNT transfer techniques are developed in order to decouple the harsh CVD growth environment from the target application devices. Two kinds of transfer medium materials, indium and polymer, have been proposed and optimized. To improve the electrical performance of the pristine CNTs, metallic coating techniques for both vertically aligned and randomly dispersed CNTs are developed and characterized. Finally, three different CNT-based interconnect scenarios: bumps, through silicon vias, and flexible conductors, are demonstrated and characterized, using the as-developed processes. The integration technologies developed in this thesis not only improve the CNT process compatibility with the conventional electronics manufacture flows, but also offers state-of-the-art electrical and mechanical performance for the non-conventional flexible and stretchable interconnect applications

NASA Tech Briefs, July 2002

Topics include: a technology focus sensors, software, electronic components and systems, materials, mechanics, machinery/automation, manufacturing, bio-medical, physical sciences, information sciences, book and reports, and a special section of Photonics Tech Briefs

Towards an on-chip power supply: Integration of micro energy harvesting and storage techniques for wireless sensor networks

The lifetime of a power supply in a sensor node of a wireless sensor network is the decisive factor in the longevity of the system. Traditional Li-ion batteries cannot fulfill the demands of sensor networks that require a long operational duration. Thus, we require a solution that produces its own electricity from its surrounding and stores it for future utility. Moreover, as the sensor node architecture is developed on complimentary metal-oxide-semiconductor technology (CMOS), the manufacture of the power supply must be compatible with it. In this thesis, we shall describe the components of an on-chip lifetime power supply that can harvest the vibrational mechanical energy through piezoelectric microcantilevers and store it in a reduced graphene oxide (rGO) based microsupercapacitor, and that is fabricated through CMOS compatible techniques. Our piezoelectric microcantilevers confirm the feasibility of fabricating micro electro- mechanical-systems (MEMS) size two-degree-of-freedom systems which can solve the major issue of small bandwidth of piezoelectric micro-energy harvesters. These devices use a cut-out trapezoidal cantilever beam to enhance the stress on the cantilever’s free end while reducing the gap remarkably between its first two eigenfrequencies in 400 - 500 Hz and 1 - 2 kHz range. The energy from the M-shaped harvesters will be stored in rGO based microsupercapacitors. These microsupercapacitors are manufactured through a fully CMOS compatible, reproducible, and reliable micromachining processes. Furthermore, we have also demonstrated an improvement in their electrochemical performance and yield of fabrication through surface roughening from iron nanoparticles. We have also examined the possibility of integrating these devices into a power management unit to fully realize a lifetime power supply for wireless sensor networks