Entanglement of spin waves among four quantum memories

Quantum networks are composed of quantum nodes that interact coherently by way of quantum channels and open a broad frontier of scientific opportunities. For example, a quantum network can serve as a `web' for connecting quantum processors for computation and communication, as well as a `simulator' for enabling investigations of quantum critical phenomena arising from interactions among the nodes mediated by the channels. The physical realization of quantum networks generically requires dynamical systems capable of generating and storing entangled states among multiple quantum memories, and of efficiently transferring stored entanglement into quantum channels for distribution across the network. While such capabilities have been demonstrated for diverse bipartite systems (i.e., N=2 quantum systems), entangled states with N > 2 have heretofore not been achieved for quantum interconnects that coherently `clock' multipartite entanglement stored in quantum memories to quantum channels. Here, we demonstrate high-fidelity measurement-induced entanglement stored in four atomic memories; user-controlled, coherent transfer of atomic entanglement to four photonic quantum channels; and the characterization of the full quadripartite entanglement by way of quantum uncertainty relations. Our work thereby provides an important tool for the distribution of multipartite entanglement across quantum networks.Comment: 4 figure

On the tailoring of CAST-32A certification guidance to real COTS multicore architectures

The use of Commercial Off-The-Shelf (COTS) multicores in real-time industry is on the rise due to multicores' potential performance increase and energy reduction. Yet, the unpredictable impact on timing of contention in shared hardware resources challenges certification. Furthermore, most safety certification standards target single-core architectures and do not provide explicit guidance for multicore processors. Recently, however, CAST-32A has been presented providing guidance for software planning, development and verification in multicores. In this paper, from a theoretical level, we provide a detailed review of CAST-32A objectives and the difficulty of reaching them under current COTS multicore design trends; at experimental level, we assess the difficulties of the application of CAST-32A to a real multicore processor, the NXP P4080.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal grant RYC-2013-14717.Peer ReviewedPostprint (author's final draft

Contention-aware performance monitoring counter support for real-time MPSoCs

Tasks running in MPSoCs experience contention delays when accessing MPSoC’s shared resources, complicating task timing analysis and deriving execution time bounds. Understanding the Actual Contention Delay (ACD) each task suffers due to other corunning tasks, and the particular hardware shared resources in which contention occurs, is of prominent importance to increase confidence on derived execution time bounds of tasks. And, whenever those bounds are violated, ACD provides information on the reasons for overruns. Unfortunately, existing MPSoC designs considered in real-time domains offer limited hardware support to measure tasks’ ACD losing all these potential benefits. In this paper we propose the Contention Cycle Stack (CCS), a mechanism that extends performance monitoring counters to track specific events that allow estimating the ACD that each task suffers from every contending task on every hardware shared resource. We build the CCS using a set of specialized low-overhead Performance Monitoring Counters for the Cobham Gaisler GR740 (NGMP) MPSoC – used in the space domain – for which we show CCS’s benefits.The research leading to these results has received funding from the European Space Agency under contracts 4000109680, 4000110157 and NPI 4000102880, and the Ministry of Science and Technology of Spain under contract TIN-2015-65316-P. Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.Peer ReviewedPostprint (author's final draft

Semi-supervised Tuning from Temporal Coherence

Recent works demonstrated the usefulness of temporal coherence to regularize supervised training or to learn invariant features with deep architectures. In particular, enforcing smooth output changes while presenting temporally-closed frames from video sequences, proved to be an effective strategy. In this paper we prove the efficacy of temporal coherence for semi-supervised incremental tuning. We show that a deep architecture, just mildly trained in a supervised manner, can progressively improve its classification accuracy, if exposed to video sequences of unlabeled data. The extent to which, in some cases, a semi-supervised tuning allows to improve classification accuracy (approaching the supervised one) is somewhat surprising. A number of control experiments pointed out the fundamental role of temporal coherence.Comment: Under review as a conference paper at ICLR 201

Surveyor landing radar test program review Final report

Test program evaluation and modifications for Surveyor radar altimeter and Doppler velocity sensor syste

On the Security of the Automatic Dependent Surveillance-Broadcast Protocol

Automatic dependent surveillance-broadcast (ADS-B) is the communications protocol currently being rolled out as part of next generation air transportation systems. As the heart of modern air traffic control, it will play an essential role in the protection of two billion passengers per year, besides being crucial to many other interest groups in aviation. The inherent lack of security measures in the ADS-B protocol has long been a topic in both the aviation circles and in the academic community. Due to recently published proof-of-concept attacks, the topic is becoming ever more pressing, especially with the deadline for mandatory implementation in most airspaces fast approaching. This survey first summarizes the attacks and problems that have been reported in relation to ADS-B security. Thereafter, it surveys both the theoretical and practical efforts which have been previously conducted concerning these issues, including possible countermeasures. In addition, the survey seeks to go beyond the current state of the art and gives a detailed assessment of security measures which have been developed more generally for related wireless networks such as sensor networks and vehicular ad hoc networks, including a taxonomy of all considered approaches.Comment: Survey, 22 Pages, 21 Figure

HACCP plan fresh fish processing Marituna

In the past regulatory authorities for food products had a duty to ensure that foods offered tothe consumer are at least safe to eat. The authorities required a positive approach of using Good Manufacturing Practices (GMP), producing food in a hygienic manner, and by inspection of finished product. It is now realised that inspection of finished product gives a poor control over the safety of foods. Therefore, since 1 January 1993, regulatory authorities in Europe required that companies take a preventative approach to safety based on the principles of Hazard Analysis and Critical Control Points (HACCP). Anyone exporting fish products to Europe or North America will have to implement a programme based on HACCP. If a company cannot demonstrate to the satisfaction of regulating agencies in importing countries that it has an effective programme operating in their processing plant, importers will not be permitted to accept the products. The United Nations food standard group Codex Alimentarius Commission has recommended HACCP's adoption as a system for ensuring the safety of foods (including finfish and shellfish) and the prevention of foodborne diseases