Variational capacitance modeling using orthogonal polynomial method

ABSTRACT In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spectral stochastic method where orthogonal polynomials are used to represent the statistical processes in a deterministic way. We first show how the variational potential coefficient matrix is represented in a first-order form using Taylor expansion and orthogonal decomposition. Then an augmented potential coefficient matrix, which consists of the coefficients of the polynomials, is derived. After that, corresponding augmented system is solved to obtain the variational capacitance values in the orthogonal polynomial form. Experimental results show that our method is two orders of magnitude faster than the recently proposed statistical capacitance extraction method based on the spectral stochastic collocation approac

Uncertainty quantification for integrated circuits: Stochastic spectral methods

Due to significant manufacturing process variations, the performance of integrated circuits (ICs) has become increasingly uncertain. Such uncertainties must be carefully quantified with efficient stochastic circuit simulators. This paper discusses the recent advances of stochastic spectral circuit simulators based on generalized polynomial chaos (gPC). Such techniques can handle both Gaussian and non-Gaussian random parameters, showing remarkable speedup over Monte Carlo for circuits with a small or medium number of parameters. We focus on the recently developed stochastic testing and the application of conventional stochastic Galerkin and stochastic collocation schemes to nonlinear circuit problems. The uncertainty quantification algorithms for static, transient and periodic steady-state simulations are presented along with some practical simulation results. Some open problems in this field are discussed.MIT Masdar Program (196F/002/707/102f/70/9374

Interconnect capacitance extraction under geometric uncertainties

Interconnects are an important constituent of any large scale integrated circuit, and accurate interconnect analysis is essential not only for post-layout verification but also for synthesis. For instance, extraction of interconnect capacitance is needed for the prediction of interconnect-induced delay, crosstalk, and other signal distortion related effects that are used to guide IC routing and floor planning. The continuous progress of semiconductor technology is leading ICs to the era of 45 nm technology and beyond. However, this progress has been associated with increasing variability during the manufacturing processes. This variability leads to stochastic variations in geometric and material parameters and has a significant impact on interconnect capacitance. It is therefore important to be able to quantify the effect of such process induced variations on interconnect capacitance. In this thesis, we have worked on a methodology towards modeling of interconnect capacitance in the presence of geometric uncertainties. More specifically, a methodology is proposed for the finite element solution of Laplace's equation for the calculation of the per-unit-length capacitance matrix of a multi-conductor interconnect structure embedded in a multi-layered insulating substrate and in the presence of statistical variation in conductor and substrate geometry. The proposed method is founded on the idea of defining a single, mean geometry, which is subsequently used with a single finite element discretization, to extract the statistics of the interconnect capacitance in an expedient fashion. We demonstrate the accuracy and efficiency of our method through its application to the extraction of capacitances in some representative geometries for IC interconnects

Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits

FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance and resistance extraction is crucial in the design and verification of Fin- FET integrated circuits. Though there are wide varieties of techniques available for parasitic extraction, FinFETs still pose tremendous challenges due to the complex geometries and user model of FinFETs. In this thesis, we propose three practical techniques for parasitic extraction of FinFET integrated circuits. The first technique we propose is to solve the dilemma that foundries and IP vendors face to protect the sensitive information which is prerequisite for accurate parasitic extraction. We propose an innovative solution to the challenge, by building a macro model around any region in 2D/3D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. The second technique we present is to reduce the truncation error introduced by the traditional Neumann boundary condition. We make a fundamental contribution to the theory of field solvers by proposing a class of absorbing boundary conditions, which when placed on the boundary of the numerical region, will act as if the region extends to infinity. As a result, we can significantly reduce the size of the numerical region, which in turn reduces the run time without sacrificing accuracy. Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM. The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example

Numerical Methods for Parasitic Extraction of Advanced Integrated Circuits

FFinFETs, also known as Fin Field Effect Transistors, are a type of non-planar transistors used in the modern integrated circuits. Fast and accurate parasitic capacitance and resistance extraction is crucial in the design and verification of Fin- FET integrated circuits. Though there are wide varieties of techniques available for parasitic extraction, FinFETs still pose tremendous challenges due to the complex geometries and user model of FinFETs. In this thesis, we propose three practical techniques for parasitic extraction of FinFET integrated circuits. The first technique we propose is to solve the dilemma that foundries and IP vendors face to protect the sensitive information which is prerequisite for accurate parasitic extraction. We propose an innovative solution to the challenge, by building a macro model around any region in 2D/3D on a circuit where foundries or IP vendors wish to hide information, yet the macro model allows accurate capacitance extraction inside and outside of the region. The second technique we present is to reduce the truncation error introduced by the traditional Neumann boundary condition. We make a fundamental contribution to the theory of field solvers by proposing a class of absorbing boundary conditions, which when placed on the boundary of the numerical region, will act as if the region extends to infinity. As a result, we can significantly reduce the size of the numerical region, which in turn reduces the run time without sacrificing accuracy. Finally, we improve the accuracy and efficiency of resistance extraction for Fin-FET with non-orthogonal resistivity interface through FVM and IFEM. The performance of FVM is comparable to FEM but with better stability since the conservation law is guaranteed. The IFEM is even better in both efficiency and mesh generation cost than other methods, including FDM, FEM and FVM. The proposed methods are based on rigorous mathematical derivations and verified through experimental results on practical example

Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

Field solver technologies for variation-aware interconnect parasitic extraction

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 207-213).Advances in integrated circuit manufacturing technologies have enabled high density onchip integration by constantly scaling down the device and interconnect feature size. As a consequence of the ongoing technology scaling (from 45nm to 32nm, 22nm and beyond), geometrical variabilities induced by the uncertainties in the manufacturing processes are becoming more significant. Indeed, the dimensions and shapes of the manufactured devices and interconnect structures may vary by up to 40% from their design intent. The effect of such variabilities on the electrical characteristics of both devices and interconnects must be accurately evaluated and accounted for during the design phase. In the last few years, there have been several attempts to develop variation-aware extraction algorithms, i.e. algorithms that evaluate the effect of geometrical variabilities on the electrical characteristics of devices and interconnects. However, most algorithms remain computationally very expensive. In this thesis the focus is on variation-aware interconnect parasitic extraction. In the first part of the thesis several discretization-based variation-aware solver techniques are developed. The first technique is a stochastic model reduction algorithm (SMOR) The SMOR guarantees that the statistical moments computed from the reduced model are the same as those of the full model. The SMOR works best for problems in which the desired electrical property is contained in an easily defined subspace.(cont.) The second technique is the combined Neumann Hermite expansion (CNHE). The CNHE combines the advantages of both the standard Neumann expansion and the standard stochastic Galerkin method to produce a very efficient extraction algorithm. The CNHE works best in problems for which the desired electrical property (e.g. impedance) is accurately expanded in terms of a low order multivariate Hermite expansion. The third technique is the stochastic dominant singular vectors method (SDSV). The SDSV uses stochastic optimization in order to sequentially determine an optimal reduced subspace, in which the solution can be accurately represented. The SDSV works best for large dimensional problems, since its complexity is almost independent of the size of the parameter space. In the second part of the thesis, several novel discretization-free variation aware extraction techniques for both resistance and capacitance extraction are developed. First we present a variation-aware floating random walk (FRW) to extract the capacitance/resistance in the presence of non-topological (edge-defined) variations. The complexity of such algorithm is almost independent of the number of varying parameters. Then we introduce the Hierarchical FRW to extract the capacitance/resistance of a very large number of topologically different structures, which are all constructed from the same set of building blocks. The complexity of such algorithm is almost independent of the total number of structures. All the proposed techniques are applied to a variety of examples, showing orders of magnitude reduction in the computational time compared to the standard approaches. In addition, we solve very large dimensional examples that are intractable when using standard approaches.by Tarek Ali El-Moselhy.Ph.D