Asynchronous techniques for new generation variation-tolerant FPGA

PhD ThesisThis thesis presents a practical scenario for asynchronous logic implementation that would benefit the modern Field-Programmable Gate Arrays (FPGAs) technology in improving reliability. A method based on Asynchronously-Assisted Logic (AAL) blocks is proposed here in order to provide the right degree of variation tolerance, preserve as much of the traditional FPGAs structure as possible, and make use of asynchrony only when necessary or beneficial for functionality. The newly proposed AAL introduces extra underlying hard-blocks that support asynchronous interaction only when needed and at minimum overhead. This has the potential to avoid the obstacles to the progress of asynchronous designs, particularly in terms of area and power overheads. The proposed approach provides a solution that is complementary to existing variation tolerance techniques such as the late-binding technique, but improves the reliability of the system as well as reducing the design’s margin headroom when implemented on programmable logic devices (PLDs) or FPGAs. The proposed method suggests the deployment of configurable AAL blocks to reinforce only the variation-critical paths (VCPs) with the help of variation maps, rather than re-mapping and re-routing. The layout level results for this method's worst case increase in the CLB’s overall size only of 6.3%. The proposed strategy retains the structure of the global interconnect resources that occupy the lion’s share of the modern FPGA’s soft fabric, and yet permits the dual-rail iv completion-detection (DR-CD) protocol without the need to globally double the interconnect resources. Simulation results of global and interconnect voltage variations demonstrate the robustness of the method

Predictive control of a Boeing 747 aircraft using an FPGA

New embedded predictive control applications call for more efficient ways of solving quadratic programs (QPs) in order to meet demanding real-time, power and cost requirements. A single precision QP-on-a-chip controller is proposed, implemented in a field-programmable gate array (FPGA) with an iterative linear solver at its core. A novel offline scaling procedure is introduced to aid the convergence of the reduced precision solver. The feasibility of the proposed approach is demonstrated with a real-time hardware-in-the-loop (HIL) experimental setup where an ML605 FPGA board controls a nonlinear model of a Boeing 747 aircraft running on a desktop PC through an Ethernet link. Simulations show that the quality of the closed-loop control and accuracy of individual solutions is competitive with a conventional double precision controller solving linear systems using a Riccati recursion.This work was supported by the EPSRC (Grants EP/G031576/1, EP/G030308/1 and EP/I012036/1) and the EU FP7 Project EMBOCON, as well as industrial support from Xilinx, the Mathworks, and the European Space Agency.IFAC Conference on Nonlinear Model Predictive Control 2012 (NMPC'12), Noordwijkerhout, the Netherlands on August 23 - 27, 2012

DUAL-RAIL GATE STRUCTURE FOR A COMPLEX DATA PATH

Dual-rail domino gates are restricted to create a reliable critical data path. According to this critical data path, the handshake circuits are greatly simplified, that provides the pipeline high throughput in addition to low power consumption. This paper presents a higher-throughput and ultralow-power asynchronous domino logic pipeline design method, targeting to latch-free and very fine-grain or gate-level design. The information pathways are comprised of a combination of dual-rail and single-rail domino gates. The 4 phase bundled-data protocol design most carefully resembles the style of synchronous circuits. Furthermore, the stable critical data path enables the adoption of single-rail domino gates within the noncritical data pathways. An 8 × 8 array style multiplier can be used for evaluating the suggested pipeline method. This saves lots of power by reduction of the overhead of logic circuits. In contrast to a bundled-data asynchronous domino logic pipeline, the suggested pipeline saves energy within the best situation and also the worst situation when processing different data patterns

低電力非同期回路の面積高効率化設計

Tohoku University亀山充隆課

Low-Power Mixed-Signal ASIC for Cryogenic SiPM Readout

L'abstract è presente nell'allegato / the abstract is in the attachmen

PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND

The primary objective of this research work is the development of a low power single-lead ECG analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient gain and frequency control mechanism and a low complexity classifier for the detecting asystole, extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the design of a compact single-lead wearable/portable devices with ultra-low-power consumption and in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an efficient automatic gain control mechanism with minimal area overhead and consuming power in the order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR), hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter design, the low pass cut-off frequency is prone to deviate from its nominal value across process and temperature variations. Therefore, post-fabrication calibration is essential, before the signal is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher frequencies into the bandwidth for classification of ECG signals, to switch to low resolution processing, hence saving power and enhances battery lifetime. Another short-coming noticed in the literature published so far is that the classification algorithm is implemented in digital domain, which turns out to be a power hungry approach. Moreover, Although analog domain implementations of QRS complexes detection schemes have been reported, they employ an external micro-controller to determine the threshold voltage. In this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a heart rate estimator is added to the above scheme. It reduces the overall system power consumption by reducing the computational burden on the DSP. The complete proposed scheme consists of (i) an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage, hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis. The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V supply. The functionality of each of the individual blocks are successfully validated using postextraction process corner simulations and through real ECG test signals taken from the PhysioNet database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the measurement results are discussed here. The analog classification scheme is successfully validated using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac

Distributed speed control for multi-three-phase motors with enhanced power sharing capabilities

This thesis describes the last three years work and the results achieved after several stages of design and experimental validation. The main result is the development of a novel sharing current controller for multi-three-phase electrical machines. The proposed regulator, called "speed-drooped" or simply "droop" controller, allows the current transient triggered by a step change within the rotating reference frame to be controlled. Since multi-three-phase systems appear to be very good candidates for future Integrated Modular Motor Drives and next transportation system challenges, the work has been set up with modularity and redundancy for next future motor drives. During the preliminary stages, the mathematical models of the droop controller have been derived and validated on a multi-drive rig with two three-phase induction motors on the same shaft at the University of Nottingham. After, while developing a new general purpose control platform for power electronics able to control up to three three-phase systems, the Vector Space Decomposition for de-coupling the mutual interactions within multi-three-phase electric motors has been studied. Thanks to it, the inductance matrix of a triple-star two poles synchronous generator at the University of Trieste, Italy, has been diagonalised. Finally, the proposed current controller has been experimentally validated on a nine-phase synchronous generator and compared with the state of the art current sharing techniques. Furthermore, a post-fault compensation strategy has been formulated and validated by means of simulation work. If compared to the state-of-the-art current sharing techniques, the "droop" regulator capability of controlling current sharing transients while keeping constant speed of the shaft has been proven and successfully demonstrated by means of Matlab/Simulink simulations and experiments on both rigs