Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs

With a unified physics-based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process-induced and global-induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon-germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature. A dual channel heterostructure consisting of strained Si/Si1-xGex on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics-based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n-channel drive currents of 0.43 and 0.98 mA/Gm, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Design Consideration And Impact Of Gate Length Variation On Junctionless Strained Double Gate MOSFET

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces

Until the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constraints in terms of gate leakage and reliability have been delaying the diminution of the equivalent oxide thickness (EOT). Concurrently, lowering the supply voltage (VDD) has become a critical necessity to reduce both the active and passive power density in integrated circuits. Hence the challenge: how to keep decreasing both gate length and supply voltage faster than the EOT without losing in terms of ON-state/OFF-state performance trade-off? Several solutions can be proposed aiming at solving this conundrum for nanoscale transistors, with architectures in rupture with the plain old Silicon-based MOSFET with doped Source and Drain invented in 1960. One approach consists in achieving an ION increase while keeping IOFF (and Vth) mostly unchanged. Specifically, two options are considered in detail in this manuscript through a review of their respective historical motivations, state-of-the-art results as well as remaining fundamental (and technological) challenges: i/ the reduction of the extrinsic parasitic resistance through the implementation of metallic Source and Drain (Schottky Barrier FET architecture); ii/ the reduction of the intrinsic channel resistance through the implementation of Germanium-based mobility boosters (Ge CMOS, compressively-strained SiGe channels, n-sSi/p-sSiGe Dual Channel co-integration). In particular, we study the case of thin films on insulator (SOI, SiGeOI, GeOI substrates), a choice justified by: the preservation of the electrostatic integrity for the targeted sub-22nm nodes; the limitation of ambipolar leakage in SBFETs; the limitation of junction leakage in (low-bandgap) Ge-based FETs. Finally, we show why, and under which conditions the association of the SBFET architecture with a Ge-based channel could be potentially advantageous with respect to conventional Si CMOS.Jusqu’au début des années 2000, les règles de scaling de Dennard ont permis de réaliser des gains en performance tout en conservant la structure de la brique de base transistor d’une génération technologique à la suivante. Cependant, cette approche conservatrice a d’ores et déjà atteint ses limites, comme en témoigne l’introduction de la contrainte mécanique pour les générations sub-130nm, et les empilements de grille métal/high-k pour les nœuds sub-65nm. Malgré l’introduction de diélectriques à forte permittivité, des limites en termes de courants de fuite de grille et de fiabilité ont ralenti la diminution de l’épaisseur équivalente d’oxyde (EOT). De façon concommitante, la diminution de la tension d’alimentation (VDD) est devenue une priorité afin de réduire la densité de puissance dissipée dans les circuits intégrés. D’où le défi actuel: comment continuer de réduire à la fois la longueur de grille et la tension d’alimentation plus rapidement que l’EOT sans pour autant dégrader le rapport de performances aux états passant et bloqué (ON et OFF) ? Diverses solutions peuvent être proposées, passant par des architectures s’éloignant du MOSFET conventionnel à canal Si avec source et drain dopés tel que défini en 1960. Une approche consiste en réaliser une augmentation du courant passant (ION) tout en laissant le courant à l’état bloqué (IOFF) et la tension de seuil (Vth) inchangés. Concrètement, deux options sont considérées en détail dans ce manuscrit à travers une revue de leurs motivations historiques respectives, les résultats de l’état de l’art ainsi que les obstacles (fondamentaux et technologiques) à leur mise en œuvre : i/ la réduction de la résistance parasite extrinsèque par l’introduction de source et drain métalliques (architecture transistor à barrière Schottky) ; ii/ la réduction de la résistance de canal intrinsèque par l’introduction de matériaux à haute mobilité à base de Germanium (CMOS Ge, canaux SiGe en contrainte compressive, co-intégration Dual Channel n-sSi/p-sSiGe). En particulier, nous étudions le cas de couches minces sur isolant (substrats SOI, SiGeOI, GeOI), un choix motivé par: la préservation de l’intégrité électrostatique pour les nœuds technologiques sub-22nm; la limitation du courant de fuite ambipolaire dans les SBFETs; la limitation du courant de fuites de jonctions dans les MOSFETs à base de Ge (qui est un matériau à faible bandgap). Enfin, nous montrons pourquoi et dans quelles conditions l’association d’une architecture SBFET et d’un canal à base de Germanium peut être avantageuse vis-à-vis du CMOS Silicium conventionnel

Nanoscale characterisation of dielectrics for advanced materials and electronic devices

PhD ThesisStrained silicon (Si) and silicon-germanium (SiGe) devices have long been recognised for their enhanced mobility and higher on-state current compared with bulk-Si transistors. However, the performance and reliability of dielectrics on strained Si/strained SiGe is usually not same as for bulk-Si. Epitaxial growth of strained Si/SiGe can induce surface roughness. The typical scale of surface roughness is generally higher than bulk-Si and can exceed the device size. Surface roughness has previously been shown to impact the electrical properties of the gate dielectric. Conventional macroscopic characterisation techniques are not capable of studying localised electrical behaviour, and thus prevent an understanding of the influence of large scale surface roughness. However scanning probe microscopy (SPM) techniques are capable of simultaneously imaging material and electrical properties. This thesis focuses on understanding the relationship between substrate induced surface roughness and the electrical performance of the overlying dielectric in high mobility strained Si/SiGe devices. SPM techniques including conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been applied to tensile strained Si and compressively strained SiGe materials and devices, suitable for enhancing electron and hole mobility, respectively. Gate leakage current, interface trap density, breakdown behaviour and dielectric thickness uniformity have been studied at the nanoscale. Data obtained by SPM has been compared with macroscopic electrical data from the same devices and found to be in good agreement. For strained Si devices exhibiting the typical crosshatch morphology, the electrical performance and reliability of the dielectric is strongly influenced by the roughness. Troughs and slopes of the crosshatch morphology lead to degraded gate leakage and trapped charge at the interface compared with peaks on the crosshatch undulations. Tensile strained Si material which does not exhibit the crosshatch undulation exhibits improved uniformity in dielectric properties. Quantitative agreement has been found for leakage at a device-level and nanoscale, when accounting for the tip area. The techniques developed can be used to study individual defects or regions on dielectrics whether grown or deposited (including high-κ) and on different substrates including strained Si on insulator (SSOI), strained Ge on insulator (SGOI), strained Ge, silicon carbide (SiC) and graphene. Strained SiGe samples with Ge content varying from 0 to 65% have also been studied. The increase in leakage and trapped charge density with increasing Ge extracted from SPM data is in good agreement with theory and macroscopic data. The techniques appear to be very sensitive, with SCM analysis detecting other dielectric related defects on a 20% Ge sample and the effects of the 65% Ge later exceeding the critical thickness (increased defects and variability in characteristics). Further applications and work to advance the use of electrical SPM techniques are also discussed. These include anti-reflective coatings, synthetic chrysotile nanotubes and sensitivity studies.Overseas Research Students Awards Scheme (ORSAS), School International Research Scholarship (SIRS), Newcastle University International Postgraduate Scholarship (NUIPS) and the Strained Si/SiGe platform grant

Filière technologique hybride InGaAs/SiGe pour applications CMOS

High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Design evolution of dual-material gate structure in cylindrical surrounding double-gate (CSDG) MOSFET using physics-based analytical modeling.

Doctoral Degree. University of KwaZulu- Natal, Durban.The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the fundamental component in present Micro and Nano-electronics device applications, such as switching, memory devices, communication devices, etc. MOSFET’s dimension has shrunk down following Moore’s law to attain high-speed operation and packing density integration. The scaling of conventional MOSFET has been the most prominent technological challenge in the past few years because the decreasing device dimensions increase the charge sharing from the source to the drain and that in turn give rises to the reduced gate-control over the channel, hot carrier induced degradation, and other SCEs. These undesired effects devaluate the device performance that compels optimum device design analysis for particular operating conditions. Therefore, several innovative device design/architectures, including Double-gate, FinFET, Surrounding gate MOSFET, etc., have been developed to mitigate device scaling challenges. Comprehensive research can be traced long for one such promising gate-all-around MOSFET, i.e., Cylindrical Surrounding Double-Gate (CSDG) MOSFET centrally hollow concentric structure, provides an additional internal control gate that improves the device electrical performance and offers easy accessibility. There have been several developments in terms of improvements, and applications of CSDG MOSFET have been practiced since after its evolution. This thesis’s work has been targeted to incorporate the gate material engineering in the CSDG structure after appropriate analysis of device physics-based modeling. In particular to the proposed structure, the electric field, pinch off capacitance, and after that thickness of the device parameters’ dependence have been mathematically derived from attaining the objective. Finally, a model based on a dual-material gate in CSDG MOSFET has been proposed. The electrical field in CSDG MOSFET has been analyzed in detail using a mathematical derivation of device physics, including the Surface-Potential, threshold voltage, and the gate-oxide capacitances of the internal and external part of the device. Further, the gate-oxide capacitance of CSDG MOSFET, particularly to the device pinch-off condition, has been derived. Since the device operation and analysis at the shorter channel are not similar to conventional long-channel MOSFETs, the depletion-width variation has been studied. The identified notion has been applied to derive the approximate numerical solution and silicon thickness inducing parameters for CSDG MOSFET to deploy the improvements in the device performance and novel design modifications. As the gate-material and gate-stack engineering is an alternative to overcome the device performance degradation by enhancing the charge transport efficiency, the CSDG MOSFET in a novel Dual-Metal Gate (DMG) structure design has been proposed and analyzed using the solution of 2D Poisson’s equations in the geometrical boundary conditions of the device. The model expressions obtained solution using the proposed structure has been compared with a single metal gate structure. Finally, it has been analyzed that the proposed model exhibits an excellent match with the analytical model. The obtained DMG device structure advances the carrier velocity and transport efficiency, resulting in the surface-potential profile caused by dissimilar gate metal work-function. The superior device characteristics obtained employing a dual-material structure in CSDG are promising and can reduce the threshold voltage roll-off, suppress the hot-carrier effects and SCEs