Pelatihan Editing Bahasa Inggris Dengan Grammarly Dan Layout Dengan Ms Word Pada Penerbit CV Persada

Penggunaan bahasa Inggris dalam dunia perbukuan nasional sudah mulai menggeliat. Namun, masih ditemui naskah-naskah yang telah diterbitkan dalam bentuk buku maupun monograf yang belum memenuhi kaidah bahasa Inggris yang baik. Penggunaan bahasa Inggris tidak terbatas pada artikel jurnal saja. Sekarang ini bentuk terbitan seperti majalah, koran, buku dan buku petunjuk serta diktat kuliah banyak menggunakan bahasa Inggris. Sebagai bahasa Internasional yang tidak dipelajari sejak dini. Bahasa Inggris menjadi kesulitan sendiri bagi penerbit yang ingin menerbitkan buku dalam bahasa Inggris. Penerbit CV Pena Persada memiliki dua masalah utama dalam proses penerbitan mereka, yakni 1) kurangnya kompetensi editor bahasa Inggris dan 2) Kurangnya penguasaan MS Word sebagai alat untuk proses layouting. Editing adalah prses yang sangat penting dalam penerbitan. Selain permasalahan editing, proses layout juga menjadi kendala besar bagi penerbit CV Pena Persada. Dengan tampilan buku yang baik dan tertata rapi maka pembaca akan merasa nyaman dalam menikmati buku. Proses layout menjadi tantangan tersendiri karena juga membutuhkan waktu yang lama dan keterampilan yang baik. Secara garis besar, solusi yang ditawarkan pada PKM ini adalah pelatihan editing bahasa Inggris dan Layout menggunakan MS Word. Pelatihan ini bertujuan untuk memberikan bekal keterampilan dalam melakukan editing bahasa Inggris menggunakan grammarly. Serta materi selanjutnya adalah teknik layout naskah buku menggunakan MS Word. Sasaran dari pelatihan ini adalah editor dan layouter dari Penerbit CV Pena Persada. Diharapkan pelatihan ini bisa meningkatkan kompetensi editor dan layouter pada CV Pena Persada sehingga mereka bisa melaksanakan proses penerbitan dengan lebih baik.

Speeding Up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach

Technical and economic factors have caused the field of physical design automation to receive increasing attention and commercialization. The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided very large scale integration (VLSI) design. The more an Integrated Circuit (IC) is scaled, the higher its packing density becomes. For example, in 2006 Intel\u27s 65-nm process technology for high performance microprocessor has a reduced gate length of 35 nanometers. In their 70-Mbit SRAM chip, there are up to 0.5 billion transistors in a 110 mm2 chip size with 3.4 GHz clock speed. New technology generations come out every two years and provide an approximate 0.7 times transistor size reduction as predicted by Moore\u27s Law. For the ultimate scaled MOSFET beyond 2015 or so, the transistor gate length is projected to be 10 nm and below. The continually increasing size of chips, measured in either area or number of transistors, and the wasted investment involving fabricating and testing faulty circuits, make layout analysis an important part of physical design automation. Layout-versus-schematic (LVS) is one of three kinds of layout analysis tools. Subcircuit extraction is the key problem to be solved in LVS. In LVS, two factors are important. One is run time, the other is identification correctness. This has created a need for computational intelligence. Fuzzy attributed graph is not only widely used in the fields of image understanding and pattern recognition, it is also useful to the fuzzy graph matching problem. Since the subcircuit extraction problem is a special case of a general-interest problem known as subgraph isomorphism, fuzzy attributed graphs are first effectively applied to the subgraph isomorphism problem. Then we provide an efficient fuzzy attributed graph algorithm based on the solution to subgraph isomorphism for the subcircuit extractio- n problem. Similarity measurement makes a significant contribution to evaluate the equivalence of two circuit graphs. To evaluate its performance, we compare fuzzy attributed graph approach with the commercial software called SubGemini, and two of the fastest approaches called DECIDE and SubHDP. We are able to achieve up to 12 times faster performance than alternatives, without loss of accurac

Multiobjective VLSI Cell Placement Using Distributed Simulated Evolution Algorithm

Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of adaptation. If properly engineered it is possible for SimE to reach near optimal solutions in lesser time then Simulated Annealing [1], [2]. Nevertheless, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up the execution of SimE algorithm is to parallelize it. This is all the more true for multi-objective cell placement, where the need to optimize conflicting objectives (interconnect wirelength, power dissipation, and timing performance) adds another level of difficulty [3]. In this paper a distributed parallel SimE algorithm is presented for multiobjective VLSI standard cell placement. Fuzzy logic is used to integrate the costs of these objectives. The algorithm presented is based on random distribution of rows to individual processors in order to partition the problem and distribute computationally intensive tasks, while also efficiently traversing the complex search space. A series of experiments are performed on ISCAS-85/89 benchmarks to compare speedup with serial implementation and other earlier proposals. Discussion on comparison with parallel implementations of other iterative heuristics is included

Grid Recognition: Classical and Parameterized Computational Perspectives

Grid graphs, and, more generally, $k\times r$ grid graphs, form one of the most basic classes of geometric graphs. Over the past few decades, a large body of works studied the (in)tractability of various computational problems on grid graphs, which often yield substantially faster algorithms than general graphs. Unfortunately, the recognition of a grid graph is particularly hard -- it was shown to be NP-hard even on trees of pathwidth 3 already in 1987. Yet, in this paper, we provide several positive results in this regard in the framework of parameterized complexity (additionally, we present new and complementary hardness results). Specifically, our contribution is threefold. First, we show that the problem is fixed-parameter tractable (FPT) parameterized by $k+\mathsf {mcc}$ where $\mathsf{mcc}$ is the maximum size of a connected component of $G$. This also implies that the problem is FPT parameterized by $\mathtt{td}+k$ where $\mathtt{td}$ is the treedepth of $G$ (to be compared with the hardness for pathwidth 2 where $k=3$). Further, we derive as a corollary that strip packing is FPT with respect to the height of the strip plus the maximum of the dimensions of the packed rectangles, which was previously only known to be in XP. Second, we present a new parameterization, denoted $a_G$, relating graph distance to geometric distance, which may be of independent interest. We show that the problem is para-NP-hard parameterized by $a_G$, but FPT parameterized by $a_G$ on trees, as well as FPT parameterized by $k+a_G$. Third, we show that the recognition of $k\times r$ grid graphs is NP-hard on graphs of pathwidth 2 where $k=3$. Moreover, when $k$ and $r$ are unrestricted, we show that the problem is NP-hard on trees of pathwidth 2, but trivially solvable in polynomial time on graphs of pathwidth 1

An Interconnection Network Topology Generation Scheme for Multicore Systems

Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade. Most common way of mapping applications to MPSoCs is by dividing the application into small tasks and representing them in the form of a task graph where the edges connecting the tasks represent the inter task communication. Task scheduling involves mapping task to processor cores so as to meet a specified deadline for the application/task graph. With increase in system complexity and application parallelism, task communication times are tending towards task execution times. Hence the NoC which forms the communication backbone for the cores plays a critical role in meeting the deadlines. In this thesis we present an approach to synthesize a minimal network connecting a set of cores in a MPSoC in the presence of deadlines. Given a task graph and a corresponding task to processor schedule, we have developed a partitioning methodology to generate an efficient interconnection network for the cores. We adopt a 2-phase design flow where we synthesize the network in first phase and in second phase we perform statistical analysis of the network thus generated. We compare our model with a simulated annealing based scheme, a static graph based greedy scheme and the standard mesh topology. The proposed solution offers significant area and performance benefits over the alternate solutions compared in this work

A Minimum Cost Path Search Algorithm Through Tile Obstacles

ABSTRACT In this paper, based on tile connection graph, we propose an efficient minimum cost path search algorithm through tile obstacles. This search algorithm is faster than previous graph based algorithm and unlike previous tile based algorithms, this algorithm finds the minimum cost path