FPGA Boot Loader and Scrubber

A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit")

Interchange of electronic design through VHDL and EIS

The need for both robust and unambiguous electronic designs is a direct requirement of the astonishing growth in design and manufacturing capability during recent years. In order to manage the plethora of designs, and have the design data both interchangeable and interoperable, the Very High Speed Integrated Circuits (VHSIC) program is developing two major standards for the electronic design community. The VHSIC Hardware Description Language (VHDL) is designed to be the lingua franca for transmission of design data between designers and their environments. The Engineering Information System (EIS) is designed to ease the integration of data betweeen diverse design automation systems. This paper describes the rationale for the necessity for these two standards and how they provide a synergistic expressive capability across the macrocosm of design environments

Structured modeling for VHDL synthesis

This report will describe a proposed modeling style for the use of the VHSIC Hardware Description Language (VHDL) in design synthesis. We will describe the operations and underlying assumptions of four design models currently understood and used in practice by designers: combinational logic, functional descriptions (involving clocked components such as counters), register transfer (data path) descriptions, and behavioral (instruction set or processor) designs. We will illustrate the various uses of the VHDL description styles (structural, dataflow and behavioral) to represent characteristics of each of these design models. Emphasis is placed on how VHDL constructs should be used in order to synthesize optimal designs

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

Implementación de procesador con bus espía y guía pedagógica : T.G 1213

El trabajo de grado, que se presenta en este documento, corresponde a la tercera implementación en hardware de PCSIM, proyecto de larga trayectoria que empezó a desarrollarse en 1999, teniendo como fin el aprendizaje y comprensión de la arquitectura de un procesador. Este proyecto se llevó a cabo sobre la segunda versión en hardware correspondiente a BINARIC (trabajo de grado), realizando un estudio a fondo del proyecto para así realizar algunas modificaciones en los temas de interrupciones y de bus espía, permitiendo así la simplificación de la estructura original para que el estudiante tenga un mayor entendimiento de la asignatura. Para el desarrollo del proyecto se empleó la metodología de diseño digital que se ha venido desarrollando en las asignaturas de Técnicas Digitales; el diseño de un sistema digital empieza por la descripción del sistema, un diagrama de bloques, descripción en AHPL (A Hardware Programming Language), descripción en VHDL (VHSIC Hardware description Language), simulación en el software de ALTER QUARTUS II versión 9.1 y finalmente, implementación sobre la FPGA (Field Programmable Gate array).The Degree workshop developed continues a huge project called PCSIM; PCSIM is an emulator of a processor which enables the student to understand the basic principles of processor architecture. It started in 1999, through the time two hardware implementations were done; nevertheless, some specifications should be modified to obtain a better system. Therefore this workshop concentrates in two important aspects to improve: the interrupt system and an external bus called “spy bus” to see the internal content of registers; the result of this upgrade consists on a simplification of the structure, for the student to have a complete conceptualization about the subject. For the development of this workshop, the use of the digital systems design methodology was an important path to follow because it permits a fast and well design; it consists of a clear system description, block diagrams, hardware description through AHPL (A Hardware Programming Language), VHDL (VHSIC Hardware description Language) description, software simulation through QUARTUS II 9.1 by ALTERA and finally, the implementation in the FPGA (Field Programmable Gate array) and therefore make tests using a logic analyzer.Ingeniero (a) ElectrónicoPregrad

Representation and matching of knowledge to design digital systems

A knowledge-based expert system is described that provides an approach to solve a problem requiring an expert with considerable domain expertise and facts about available digital hardware building blocks. To design digital hardware systems from their high level VHDL (Very High Speed Integrated Circuit Hardware Description Language) representation to their finished form, a special data representation is required. This data representation as well as the functioning of the overall system is described

CAR TRACTION CONTROL SYSTEM

This project explores the potential of implementing fuzzy logic algorithm for traction control system using VHDL. Previously, the project on car traction control was done by simulation using fuzzy logic approach. The Fuzzy Logic Toolbox in MATLAB software is used to create simulation for fuzzy logic system. The challenge of the project is to design the control system using hardware description language for future implementation on hardware using FPGA. Fuzzy logic controller provides optimum control according to the conditions specify. It is useful when the driving condition is uncontrolled. The core programming language which will be used as the hardware description language is VHSIC Hardware Description Language (VHDL). VHDL is used in FPGA - based implementation. The methodology includes designing the fuzzy logic controller, development of the algorithm and codes programming. After that, the following phase includes testing and troubleshooting. Lastly, carry out the documentation. In conclusion, it is possible to develop the algorithm for fuzzy - based car traction control system using VHDL. The implementation of the control system using VHDL is viable for future implementation onto FPGA. Thus the performance of the car traction control would be enhance

VHDL Implementation of High Performance and Dynamically Configured Multi-port Cache Memory

This project presents the implementation of 64x64 multi-port dynamically configured SRAM in VHDL (VHSIC hardware description language). It employs isolation nodes and dynamic memory partitioning algorithm to facilitate simultaneous multi-port accesses without duplicating bit-lines. VHDL test-bench is developed to verify the functionality of the dynamically configured memory. Results demonstrate that critical memory operations such as "read miss", "write miss" and "write bypass" can be performed using newly proposed low power, area efficient dynamically configured memory