TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA

Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design. MCMs are defined at the various layers of the hardware-software stack, requiring thoroughly verified specifications, compilers, and implementations at the interfaces between layers. Current verification techniques evaluate segments of the system stack in isolation, such as proving compiler mappings from a high-level language (HLL) to an ISA or proving validity of a microarchitectural implementation of an ISA. This paper makes a case for full-stack MCM verification and provides a toolflow, TriCheck, capable of verifying that the HLL, compiler, ISA, and implementation collectively uphold MCM requirements. The work showcases TriCheck's ability to evaluate a proposed ISA MCM in order to ensure that each layer and each mapping is correct and complete. Specifically, we apply TriCheck to the open source RISC-V ISA, seeking to verify accurate, efficient, and legal compilations from C11. We uncover under-specifications and potential inefficiencies in the current RISC-V ISA documentation and identify possible solutions for each. As an example, we find that a RISC-V-compliant microarchitecture allows 144 outcomes forbidden by C11 to be observed out of 1,701 litmus tests examined. Overall, this paper demonstrates the necessity of full-stack verification for detecting MCM-related bugs in the hardware-software stack.Comment: Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating System

Modeling and analysis of semiconductor manufacturing processes using petri nets

This thesis addresses the issues in modeling and analysis of multichip module (MCM) manufacturing processes using Petri nets. Building such graphical and mathematical models is a crucial step to understand MCM technologies and to enhance their application scope. In this thesis, the application of Petri nets is presented with top-down and bottom-up approaches. The theory of Petri nets is summarized with its basic notations and properties at first. After that, the capability of calculating and analyzing Petri nets with deterministic timing information is extended to meet the requirements of the MCM models. Then, using top-down refining and system decomposition, MCM models are built from an abstract point to concrete systems with timing information. In this process, reduction theory based on a multiple-input-single-output modules for deterministic Petri nets is applied to analyze the cycle time of Petri net models. Besides, this thesis is of significance in its use of the reduction theory which is derived for timed marked graphs - an important class of Petri nets

Optoelectronic devices and packaging for information photonics

This thesis studies optoelectronic devices and the integration of these components onto optoelectronic multi chip modules (OE-MCMs) using a combination of packaging techniques. For this project, (1×12) array photodetectors were developed using PIN diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250μm, operated at a wavelength of 850nm. Optical characterisation experiments of two types of detector arrays (shoe and ring) were successfully performed. Overall, the shoe devices achieved more consistent results in comparison with ring diodes, i.e. lower dark current and series resistance values. A decision was made to choose the shoe design for implementation into the high speed systems demonstrator. The (1x12) VCSEL array devices were the optical sources used in my research. This was an identical array at 250μm pitch configuration used in order to match the photodetector array. These devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was successfully conducted, which provided good beam profile analysis and I-V-P measurements of the VCSEL array. This was then implemented into a simple demonstrator system, where eye diagrams examined the systems performance and characteristics of the full system and showed positive results. An explanation was given of the following optoelectronic bonding techniques: Wire bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold micro-post technology were looked into and discussed. Experimental work implementing these methods on packaging the optoelectronic devices was successfully conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM was successfully performed. Electrical tests were successfully carried out on the flip chip bonded VCSEL and Photodetector arrays. These results verified that the devices attached on the MCM achieved good electrical performance and reliable bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs. The aim was to initially power up the mixed signal chip (VCSEL driver), and then observe the VCSEL output

Development and Packaging of Microsystems Using Foundry Services

Micro-electro-mechanical systems (MEMS) are a new and rapidly growing field of research. Several advances to the MEMS state of the art were achieved through design and characterization of novel devices. Empirical and theoretical model of polysilicon thermal actuators were developed to understand their behavior. The most extensive investigation of the Multi-User MEMS Processes (MUMPs) polysilicon resistivity was also performed. The first published value for the thermal coefficient of resistivity (TCR) of the MUMPs Poly 1 layer was determined as 1.25 x 10(exp -3)/K. The sheet resistance of the MUMPs polysilicon layers was found to be dependent on linewidth due to presence or absence of lateral phosphorus diffusion. The functional integration of MEMS with CMOS was demonstrated through the design of automated positioning and assembly systems, and a new power averaging scheme was devised. Packaging of MEMS using foundry multichip modules (MCMs) was shown to be a feasible approach to physical integration of MEMS with microelectronics. MEMS test die were packaged using Micro Module Systems MCM-D and General Electric High Density Intercounect and Chip-on-Flex MCM foundries. Xenon difluoride (XeF2) was found to be an excellent post-packaging etchant for bulk micromachined MEMS. For surface micromachining, hydrofluoric acid (HF) can be used

Key cell cycle regulators are implicated in both proliferative and direct glia-to-neuron cell fate switches in C. elegans

In the vertebrate nervous system, stably differentiated quiescent radial glial cells act as neural progenitors, for the first time we describe the production of neurons from glia outside of vertebrate models. Here we show that two sets of differentiated glial cells are capable of sex-specifically producing neurons in the male C. elegans. The two glia-to-neuron switches in cell fate, occur by distinct developmental mechanisms; the amphid socket (AMso) glial cells, undergo asymmetric division to produce the interneurons, the mystery cells of the male (MCMs), while the phasmid socket 1 (PHso1) glial cells directly transdifferentiate into the sensory phasmid neurons D (PHDs). In order to identify genetic factors that regulate the production of the MCMs, we have isolated nine no mystery cell (nom) mutants from a GFP-based forward genetic screen, in which the MCMs fail to be specified. Using a novel mapping-by-sequencing method, designed for male specific phenotypes, we find that two mutant alleles nom-5(drp5) and nom-8(drp8) which block AMso division, map to the cdk-4 locus on the X chromosome. Genetic analysis by rescue and complementation confirms they are alleles of cdk-4. CDK-4 is a key cell cycle regulator and intriguingly, although cdk-4 is required for all postembryonic cell divisions cdk-4(drp5) and cdk-4(drp8) present no obvious pleiotropies, hinting that novel cell cycle pathways may be involved in this specific division. The development of the MCMs and PHD share molecular features in common with vertebrate neural development, such as the expression of hlh-14, the homologue of the proneural factor ASCL1. Also, analysis of cki-1, a commonly used marker of cell cycle quiescence and G1/S regulator, shows that it is strongly expressed in both the AMso and PHso1 throughout their life prior to the production of neurons. A further surprising finding is that S-phase genes are expressed during the direct PHso1-to-PHD transdifferentiation. The role of S-phase genes in a direct transdifferentiation, that may not require DNA synthesis, is unknown. An understanding of fate plasticity is an often overlooked but key component to the processes of neurogenesis from glia, this model promises to deepen our understanding. How the progenitor cells of neurons control their ability to either re-enter or withdraw from the cell cycle and how this decision is integrated with the terminal differentiation process is an outstanding question. To this end we begin to establish the C. elegans male as a model in which to study the molecular mechanisms of late-in-development cell fate plasticity at a single cell level

Contributions to the performance of thin film capacitors for high reliability applications

Capacitors are critical devices in microelectronic assemblies that must be incorporated into electronic systems through a variety of ways such as integrated or discrete devices. This work has developed new thin film capacitors deposited directly onto multichip module or printed circuit board surfaces to benefit from closer integration that enhances system performance for use in high reliability applications. The capacitors serve as filters or provide tuning and energy storage functions. Unexpected performance was observed during development that included low adhesion of the films to the substrates, higher effective dielectric constants than reported in literature, and low yields. Three publications resulted from this work with Paper I presenting a study of thin films on low temperature cofired ceramic (LTCC) and their reliability for multiple functions. The thin film and LTCC system are modeled with results suggesting a mechanism of enhancing thin film adhesion to the LTCC through a combination film composition and surface modification. Paper II presents measurements of dielectric properties of thin film capacitors on LTCC. Multiple mechanisms are detailed that contribute to the measured dielectric constant values of the capacitors. One case is modeled to determine the extent of dielectric constant enhancement from fringe fields related to capacitor dimensions. Paper III describes the behavior of thin film capacitors with varying electrode compositions and configurations. Trends are observed that suggest energy band overlap and electrode work functions are influential in dielectric properties and yield of the capacitors. A preferred electrode composition and configuration is suggested based on the capacitor performance --Abstract, page iii

JTEC Panel report on electronic manufacturing and packaging in Japan

This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies

Automatically Comparing Memory Consistency Models

A memory consistency model (MCM) is the part of a programming language or computer architecture specification that defines which values can legally be read from shared memory locations. Because MCMs take into account various optimisations employed by archi- tectures and compilers, they are often complex and counterintu- itive, which makes them challenging to design and to understand. We identify four tasks involved in designing and understanding MCMs: generating conformance tests, distinguishing two MCMs, checking compiler optimisations, and checking compiler mappings. We show that all four tasks are instances of a general constraint-satisfaction problem to which the solution is either a program or a pair of programs. Although this problem is intractable for automatic solvers when phrased over programs directly, we show how to solve analogous constraints over program executions, and then construct programs that satisfy the original constraints. Our technique, which is implemented in the Alloy modelling framework, is illustrated on several software- and architecture-level MCMs, both axiomatically and operationally defined. We automatically recreate several known results, often in a simpler form, including: distinctions between variants of the C11 MCM; a failure of the ‘SC-DRF guarantee’ in an early C11 draft; that x86 is ‘multi-copy atomic’ and Power is not; bugs in common C11 compiler optimisations; and bugs in a compiler mapping from OpenCL to AMD-style GPUs. We also use our technique to develop and validate a new MCM for NVIDIA GPUs that supports a natural mapping from OpenCL

Development of the control system of the ALICE Transition Radiation Detector and of a test environment for quality-assurance of its front-end electronics

Im Rahmen dieser Arbeit wurde das Detektor-Kontroll-System (DCS) für den Übergangsstrahlungsdetektor (TRD) des ALICE Experiments am Large Hadron Collider entwickelt. Das TRD Kontrollsystem ist vollständig implementiert als eine detektororientierte Hierarchie von Objekten, welche sich wie End-Zustandsautomaten verhalten. Es kontrolliert und überwacht über 65 tausend front-end Elektronik (FEE) Einheiten, einige hundert low-voltage und eintausend high-voltage Kanäle, sowie weitere Subsysteme wie Kühlung und Gasversorgung. Die Inbetriebnahme des TRD Kontrollsystems fand während mehrerer Datennahmen mit ALICE unter Verwendung von Ereignissen aus der kosmischen Strahlung statt. In einem weiteren Teil dieser Arbeit wurde ein Test-setup zur Qualitätssicherung der Massenproduktion von über viertausend FEE Readout-boards mit insgesamt 1.2 Millionen elektronischen Auslesekanälen des TRD entwickelt. Die Hardware- und Softwarekomponenten werden im Detail beschrieben. Zusätzlich wurde vorher eine Reihe von Leistungsuntersuchungen durchgeführt, welche die Strahlungstoleranz des TRAP-chips überprüft, der den Haupt\-bestandteil der TRD-FEE darstellt