A VLSI synthesis of a Reed-Solomon processor for digital communication systems

The Reed-Solomon codes have been widely used in digital communication systems such as computer networks, satellites, VCRs, mobile communications and high- definition television (HDTV), in order to protect digital data against erasures, random and burst errors during transmission. Since the encoding and decoding algorithms for such codes are computationally intensive, special purpose hardware implementations are often required to meet the real time requirements. -- One motivation for this thesis is to investigate and introduce reconfigurable Galois field arithmetic structures which exploit the symmetric properties of available architectures. Another is to design and implement an RS encoder/decoder ASIC which can support a wide family of RS codes. -- An m-programmable Galois field multiplier which uses the standard basis representation of the elements is first introduced. It is then demonstrated that the exponentiator can be used to implement a fast inverter which outperforms the available inverters in GF(2m). Using these basic structures, an ASIC design and synthesis of a reconfigurable Reed-Solomon encoder/decoder processor which implements a large family of RS codes is proposed. The design is parameterized in terms of the block length n, Galois field symbol size m, and error correction capability t for the various RS codes. The design has been captured using the VHDL hardware description language and mapped onto CMOS standard cells available in the 0.8-µm BiCMOS design kits for Cadence and Synopsys tools. The experimental chip contains 218,206 logic gates and supports values of the Galois field symbol size m = 3,4,5,6,7,8 and error correction capability t = 1,2,3, ..., 16. Thus, the block length n is variable from 7 to 255. Error correction t and Galois field symbol size m are pin-selectable. -- Since low design complexity and high throughput are desired in the VLSI chip, the algebraic decoding technique has been investigated instead of the time or transform domain. The encoder uses a self-reciprocal generator polynomial which structures the codewords in a systematic form. At the beginning of the decoding process, received words are initially stored in the first-in-first-out (FIFO) buffer as they enter the syndrome module. The Berlekemp-Massey algorithm is used to determine both the error locator and error evaluator polynomials. The Chien Search and Forney's algorithms operate sequentially to solve for the error locations and error values respectively. The error values are exclusive or-ed with the buffered messages in order to correct the errors, as the processed data leave the chip

The Telecommunications and Data Acquisition Progress Journal

Developments in Earth based radio technology are reported. The Deep Space Network, radio interferometry, and observation of celestial radio sources are covered

The Telecommunications and Data Acquisition Report

Developments in programs managed by the Jet Propulsion Laboratory's Office of Telecommunications and Data acquisition are discussed. Space communications, radio antennas, the Deep Space Network, antenna design, Project SETI, seismology, coding, very large scale integration, downlinking, and demodulation are among the topics covered

Network-Coded Multiple Access

This paper proposes and experimentally demonstrates a first wireless local area network (WLAN) system that jointly exploits physical-layer network coding (PNC) and multiuser decoding (MUD) to boost system throughput. We refer to this multiple access mode as Network-Coded Multiple Access (NCMA). Prior studies on PNC mostly focused on relay networks. NCMA is the first realized multiple access scheme that establishes the usefulness of PNC in a non-relay setting. NCMA allows multiple nodes to transmit simultaneously to the access point (AP) to boost throughput. In the non-relay setting, when two nodes A and B transmit to the AP simultaneously, the AP aims to obtain both packet A and packet B rather than their network-coded packet. An interesting question is whether network coding, specifically PNC which extracts packet (A XOR B), can still be useful in such a setting. We provide an affirmative answer to this question with a novel two-layer decoding approach amenable to real-time implementation. Our USRP prototype indicates that NCMA can boost throughput by 100% in the medium-high SNR regime (>=10dB). We believe further throughput enhancement is possible by allowing more than two users to transmit together

NASA SERC 1990 Symposium on VLSI Design

This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools

Design and Validation of a Software Defined Radio Testbed for DVB-T Transmission

This paper describes the design and validation of a Software Defined Radio (SDR) testbed, which can be used for Digital Television transmission using the Digital Video Broadcasting - Terrestrial (DVB-T) standard. In order to generate a DVB-T-compliant signal with low computational complexity, we design an SDR architecture that uses the C/C++ language and exploits multithreading and vectorized instructions. Then, we transmit the generated DVB-T signal in real time, using a common PC equipped with multicore central processing units (CPUs) and a commercially available SDR modem board. The proposed SDR architecture has been validated using fixed TV sets, and portable receivers. Our results show that the proposed SDR architecture for DVB-T transmission is a low-cost low-complexity solution that, in the worst case, only requires less than 22% of CPU load and less than 170 MB of memory usage, on a 3.0 GHz Core i7 processor. In addition, using the same SDR modem board, we design an off-line software receiver that also performs time synchronization and carrier frequency offset estimation and compensation

Experimental Study of Multirate Margin in Software Defined Multirate Radio

Due to the recent development of spectrally-efficient modulation schemes, IEEE 802.11 Wifi and IEEE 802.16 WiMax radios support wireless communication at multiple bit rates. While high-rate transmission allows delivering more information in less time, the corresponding performance improvement is less than expected due to the PHY- and MAC-layer overheads, imposed by the 802.11/16 standards. This is particularly true in wireless ad hoc networks as there exist rate-distance and rate-hop count tradeoffs. The concept of multi-rate margin is proposed in this thesis, which exploits the difference in communication characteristics at different rates and serves as the fundamental ingredient for an opportunistic transmission protocol, targeted to meliorate the ad hoc mobile wireless network performance. In this thesis, the multi-rate margin is analyzed with theoretical derivation, perceived with simulation result using MATLAB and observed through real world testing using USRP and GNU Radio, which is a recent implementation of Software Defined Radi

Tutorial on Reed-Solomon error correction coding

This tutorial attempts to provide a frank, step-by-step approach to Reed-Solomon (RS) error correction coding. RS encoding and RS decoding both with and without erasing code symbols are emphasized. There is no need to present rigorous proofs and extreme mathematical detail. Rather, the simple concepts of groups and fields, specifically Galois fields, are presented with a minimum of complexity. Before RS codes are presented, other block codes are presented as a technical introduction into coding. A primitive (15, 9) RS coding example is then completely developed from start to finish, demonstrating the encoding and decoding calculations and a derivation of the famous error-locator polynomial. The objective is to present practical information about Reed-Solomon coding in a manner such that it can be easily understood