Surface Potential-Based Polycrystalline-Silicon Thin-Film Transistors Compact Model by Nonequilibrium Approach

We propose a surface potential-based polycrystalline silicon thin-film transistors (poly-Si TFTs) compact model considering a nonequilibrium state. A drain current model considers grain boundary (GB) trap-related physical phenomena: composite mobility of GB and intragrain, GB bias-induced mobility modulation, transient behavior because of carrier capture and emission at GBs, pinch off voltage lowering, and GB trap-assisted leakage current. Besides, photoinduced current behavior is also considered by introducing quasi-Fermi potential. A capacitance model is derived from physically partitioned terminal charges and coupled to the drain current. This compact model allows us to accurately simulate static characteristics of various types of poly-Si TFTs, including temperature and luminance dependence. Furthermore, it succeeded to simulate frequency dependence of circuit performance derived from the trap-related transient behavior, which was verified by evaluating delay time in a 21-stage inverter chain

Semi-empirical RF MOST model for CMOS 65 nm technologies: theory, extraction method and validation

This paper presents a simple but accurate semi-empirical model especially focused on 65 nm MOST (MOS transistor) technologies and radio-frequency (RF) applications. It is obtained by means of simple dc and noise simulations extracted over a constrained set of MOSTs. The fundamental variable of the model is the MOST transconductance to current drain ratio gm/ID. Specifically it comprises the large signal DC normalized current, all conductances and transconductances and the normalized intrinsic capacitances. As well, noise MOST characteristics of flicker noise, white noise and MOST corner frequency description are provided. To validate the referred model the widely utilized cascoded common source low noise amplifier (CS-LNA), in 2.5 GHz and 5.3 GHz RF applications is picked. For the presented set of designs different gm/ID ratios are considered. Finally, the computed results are assessed by comparing with the outcomes of electrical simulations.Ministerio de Economía y Competitividad TEC2011-2830

SPICE MODELING OF IONIZING RADIATION EFFECTS IN CMOS DEVICES

Electric characteristics of devices in advanced CMOS technologies change over the time because of the impact of the ionizing radiation effects. Device aging is caused by cumulative contribution of generation of defects in the gate oxide and/or at the interface silicon-oxide. The concentration of these defects is time and bias-dependent values. Existing models include these effects through constant shift of voltage threshold. A method for including ionizing radiation effects in Spice models of MOS transistor and FiNFET, based on an auxiliary diode circuit using for derivation of values of surface potential, that also calculates the correction time-dependent voltage due to concentration of trapped charges, is shown in this paper

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts