VLSI design of configurable low-power coarse-grained array architecture

Biomedical signal acquisition from in- or on-body sensors often requires local (on-node) low-level pre-processing before the data are sent to a remote node for aggregation and further processing. Local processing is required for many different operations, which include signal cleanup (noise removal), sensor calibration, event detection and data compression. In this environment, processing is subject to aggressive energy consumption restrictions, while often operating under real-time requirements. These conflicting requirements impose the use of dedicated circuits addressing a very specific task or the use of domain-specific customization to obtain significant gains in power efficiency. However, economic and time-to-market constraints often make the development or use of application-specific platforms very risky.One way to address these challenges is to develop a sensor node with a general-purpose architecture combining a low-power, low-performance general microprocessor or micro-controller with a coarse-grained reconfigurable array (CGRA) acting as an accelerator. A CGRA consists of a fixed number of processing units (e.g., ALUs) whose function and interconnections are determined by some configuration data.The objective of this work is to create an RTL-level description of a low-power CGRA of ALUs and produce a low-power VLSI (standard cell) implementation, that supports power-saving features.The CGRA implementation should use as few resources as possible and fully exploit the intended operation environment. The design will be evaluated with a set of simple signal processing task

The Design And Vlsi Implementation Of Digital Arithmatic Processors - A Case Study Of A Generalized Pipeline Cellular Array

A generalized pipeline array appeared in IEEE transaction in 1974. The array appeared in a few textbooks on computer arithmetic. From time to time, a number of papers appeared which reflected the modifications of this array. The objective of this thesis is to present the design and VLSI implementation of this array, which can add, subtract, multiply, divide, square and square root of binary numbers. In this thesis, we suggest a step-by-step procedure by which the design can be sent to MOSIS and to get the fabricated chip back. The array has been extended from 5 rows to 7 rows so that the extended operations can be performed. In particular, a procedure is developed by which the design and the implementation methodologies are suitable for 40 pin and 500 nm technologies. An algorithm has been developed by which one can predict and advance the maximum size and performance of the array. In addition, to increase data processing throughput, the extension of pipelining is conducted based on the original design. It is hoped that the design and implementation done here will go a long way in the development of advanced processors

Ion camera development for real–time acquisition of localised pH responses using the CMOS based 64×64–pixel ISFET sensor array technology

This thesis presents the development and test of an integrated ion camera chip for monitoring highly localised ion fluxes of electrochemical processes using an ion sensitive sensor array. Ionic concentration fluctuations are shown to travel across the sensor array as a result of citric acid injection and the BZ-reaction. The imaging capability of non-equilibrium chemical activities is also demonstrated monitoring self-assembling micrometre sized polyoxometalate tubular and membranous architectures. The sufficient spatial resolution for the visualisation of the 10-60 µm wide growing trajectories is provided by the dense sensor array containing 64×64 pixels. In the case of citric acid injection and the BZ-reaction the ion camera chip is shown to be able to resolve pH differences with resolution as low as the area of one pixel. As a result of the transient and volatile ionic fluxes high time resolution is required, thus the signal capturing can be performed in real.time at the maximum sampling rate of 40 µs per pixel, 10.2 ms per array. The extracted sensor data are reconstructed into ionic images and thus the ionic activities can be displayed as individual figures as well as continuous video recordings. This chip is the first prototype in the envisioned establishment of a fully automated CMOS based ion camera system which would be able to image the invisible activity of ions using a single microchip. In addition the capability of detecting ultra-low level pH oscillations in the extracellular space is demonstrated using cells of the slime mould organism. The detected pH oscillations with extent of ~0.022 pH furthermore raise the potential for observing fluctuations of ion currents in cell based tissue environments. The intrinsic noise of the sensor devices are measured to observe noise effect on the detected low level signals. It is experimentally shown that the used ion sensitive circuits, similarly to CMOS, also demonstrate 1/f noise. In addition the reference bias and pH sensitivity of the measured noise is confirmed. Corresponding to the measurement results the noise contribution is approximated with a 28.2 µV peak-to-peak level and related to the 450 µV �+/- 70 µV peak-to-peak oscillations amplitudes of the slime mould. Thus a maximum intrinsic noise contribution of 6.2 �+/- 1.2 % is calculated. A H+ flickering hypothesis is also presented that correlates the pH fluctuations on the surface of the device with the intrinsic 1/f noise. The ion camera chip was fabricated in an unmodified 4-metal 0.35 µm CMOS process and the ionic imaging technology was based on a 64�×64-pixel ion sensitive field effect transistor (ISFET) array. The high-speed and synchronous operation of the 4096 ISFET sensors occupying 715.8×715.8 µm space provided a spatial resolution as low as one pixel. Each pixel contained 4 transistors with 10.2×10.2 µm layout dimensions and the pixels were separated by a 1 µm separation gap. The ion sensitive silicon nitride based passivation layer was in contact with the floating gates of the ISFET sensors. It allowed the capacitive measurements of localised changes in the ionic concentrations, e.g. pH, pNa, on the surface of the chip. The device showed an average ionic sensitivity of 20 mV/pH and 9 mV/pNa. The packaging and encapsulation was carried out using PGA-100 chip carriers and two-component epoxies. Custom designed printed circuit boards (PCBs) were used to provide interface between the ISFET array chip and the data acquisition system. The data acquisition and extraction part of the developed software system was based on LabVIEW, the data processing was carried out on Matlab platform

Low voltage techniques for pipelined analog-to-digital converters

To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance. This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a fully-differential implementation of the OpAmp Reset Switching Technique (ORST) as a suitable low voltage design solution. The technique uses a true fully differential MDAC structure with a switching common-mode feedback to achieve increased linearity and noise performance over the previously published ORST. A pipelined ADC test chip is designed to implement the fully differential ORST technique as a proof of concept. The design also includes a simple, low power input sampling network that also allows an increased input signal range and saves power by removing the dedicated, front-end S/H. Prototype performance demonstrates the fully differential ORST and shows sampling speeds of up to 60 MS/s, 51.4 dB SNR, 58.8 dB SFDR, and 49.7 dB SNDR for an 8-bit ENOB in a 0.18 μm CMOS process with a 1 V supply. Little change in distortion is observed up to 90 MHz input frequency, demonstrating operation without a S/H

ANALYZING URBAN GROWTH AND MANAGEMENT FOR THE CITY OF TRIPOLI, LIBYA

This study focuses on the urban growth and management of the city of Tripoli, Libya with an emphasis on the contribution of the economic, social, and political factors in urbanization. Despite the fact that urban planning authorities established and developed several projects and planning generation series, there have been such issues and challenges tackling the fast growth of urban centers, which resulted in population concentration and shortage of services such as housing. This has led to a massive and random expansion in urban areas, which has eliminated huge agricultural and green spaces in favor of new urban areas. Based on archival data, interviews, and very close knowledge of the study area, I argue that there have been constant difficulties in managing and controlling the urban expansion within urban centers in general and Tripoli in particular. In this study, I examined the role of each factor of urban growth and urbanization in the Libyan case compared to Africa in general in line with the theories of Myers (2011), Beall and Fox (2009), Forester (1998), and others. Furthermore, I addressed the question of whether the rapid growth of the city of Tripoli is related to the urban policy and planning strategies through the emphasis on laws and regulations. Planners have stressed reforming the urban planning system and developing a solid relationship with political power and enhancing the role of technology toward developing a modern planning system. Finally, I attempted to focus on the involvement of politics in the urban planning system, which was inspired by the deep and strong role of the social system. There has been a remarkable degree of social and political interference in planning, which has weakened the democratic process and resulted in very corrupt and disorganized urban planning practices, which will be a very important topic for further research. The three GIS data layers used for this research is included in the supplementary files

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Analog microelectronic emulation for dynamic power system computation

Power system dynamic simulators can be classified according to multiple criteria, including speed, precision, cost and modularity (topology, characteristics and model). Existing simulators are based on time-consuming numeric algorithms, which provide very precise results. But the evolution of the power grid constantly changes the requirements for simulators. In fact, power consumption is steadily increasing; therefore, the power system is always operating closer to its limits. Moreover, focus is put on decentralized and stochastic green energy sources, leading to a much more complex and less predictable power system. In order to guarantee security of supply under these conditions, real-time control and online security assessment are of the utmost importance. The main requirement for power system simulators in this context thus becomes the simulation time. The simulator has to be able to reproduce power system phenomena much faster than their real-time duration. An effective way to accelerate computation time of power system stability simulators is based on analog emulation of the power system grid. The idea is to avoid the heavy, time-consuming numerical matrix calculations of the grid by using an instantaneous analog Kirchhoff grid, with which computation becomes intrinsically parallel and the simulation time independent of the power system topology size. An overview of the power system computation history and the evolution of microelectronics highlights that the renaissance of dedicated analog computation is justified. Modern VLSI technologies can overcome the drawbacks which caused the disappearance of analog computation units in the 1960s. This work addresses therefore the development of a power system emulation approach from its theoretical principles to the behavioral design and the microelectronic implementation of a first demonstrator. The approach used in this research is called AC emulation approach and is based on a one-to-one mapping of components of the real power system (generator, load and transmission line) by emulating their behavior on a CMOS microelectronic integrated circuit (ASIC). The signals propagating on the emulated grid are the shrunk and downscaled current and voltage waves of the real power system. The uniqueness of this emulation approach is that frequency dependence of the signals is preserved. Therefore, the range of phenomena that can be emulated with an AC emulator depends only on the implemented models. Within the framework of this thesis, we restrict our developments to transient stability analysis, as our main focus is put on emulation speed. v We provide behavioral AC emulation models for the three main power system components. Thereby, special attention is paid to the generator model, which is shown to introduce a systematic error. This error is analyzed and reduced by model adaptation. Behavioral simulation results validate the developed models. Moreover, we suggest custom programmable analog building blocks for the implementation of the proposed behavioral models. During their design, application specific requirements, as well as imperfections, calibration, mismatch and process-variation aspects, are taken into account. In particular, the design of the tunable floating inductance used in all three AC emulation models is discussed in detail. In fact, major design challenges have to be addressed in order to achieve an inductance suitable for our application. Finally, a first AC emulation demonstrator is presented. A benchmark using a fixed two- machine topology has been implemented using a 0.35μm 3.3V CMOS technology. The characteristics of the emulated components (i.e. generators and transmission lines) are reprogrammable, allowing short circuits to be emulated at different distances from the generator. The emulated phenomena are shown to be 10′000 times faster than real time, therefore proving the high-speed capabilities of AC emulation

CMOS system for high throughput fluorescence lifetime sensing using time correlated single photon counting

Fluorescence lifetime sensing using time correlated single photon counting (TCSPC) is a key analytical tool for molecular and cell biology research, medical diagnosis and pharmacological development. However, commercially available TCSPC equipment is bulky, expensive and power hungry, typically requiring iterative software post-processing to calculate the fluorescence lifetime. Furthermore, the technique is restrictively slow due to a low photon throughput limit which is necessary to avoid distortions caused by TCSPC pile-up. An investigation into CMOS compatible multimodule architectures to miniaturise the standard TCSPC set up, allow an increase in photon throughput by overcoming the TCSPC pile-up limit, and provide fluorescence lifetime calculations in real-time is presented. The investigation verifies the operation of the architectures and leads to the selection of optimal parameters for the number of detectors and timing channels required to overcome the TCSPC pile-up limit by at least an order of magnitude. The parameters are used to implement a low power miniaturised sensor in a 130 nm CMOS process, combining single photon detection, multiple channel timing and embedded pre-processing of the fluorescence lifetime, all within a silicon area of < 2 mm2. Single photon detection is achieved using an array of single photon avalanche diodes (SPADs) arranged in a digital silicon photomultiplier (SiPM) architecture with a 10 % fill-factor and a compressed 250 ps output pulse, which provides a photon throughput of > 700 MHz. An array of time-interleaved time-to-digital converters (TI-TDCs) with 50 ps resolution and no processing dead-time records up to eight photon events during each excitation period, significantly reducing the effect of TCSPC pile-up. The TCSPC data is then processed using an embedded centre-of-mass method (CMM) pre-calculation to produce single exponential fluorescence lifetime estimations in real-time. The combination of high photon throughput and real-time calculation enables advances in applications such as fluorescence lifetime imaging microscopy (FLIM) and time domain fluorescence lifetime activated cell sorting. To demonstrate this, the device is validated in practical bulk sample fluorescence lifetime, FLIM and simulated flow based experiments. Photon throughputs in excess of the excitation frequency are demonstrated for a range of organic and inorganic fluorophores for minimal error in lifetime calculation by CMM (< 5 %)

The neurobehavioral effects of occupational exposure to organic solvents in Hong Kong printing workers.

Song Hong.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.Includes bibliographical references (leaves ).Abstracts in English and Chinese; questionnaire in Chinese.Abstract (English) --- p.iAbstract (Chinese) --- p.ivAcknowledgments --- p.viTable of Contents --- p.viiList of tables --- p.xChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Printing industry and organic solvents exposure --- p.1Chapter 1.2 --- Risk of low level exposures to organic solvents --- p.2Chapter 1.3 --- Using neurobehavioral methods to study the subclinical effects --- p.3Chapter Chapter 2 --- Literature review --- p.4Chapter 2.1 --- Organic solvents and neurobehavioral impairment --- p.4Chapter 2.2 --- Methodology of Neurobehavioral Test --- p.6Chapter 2.2.1 --- Criteria for selecting test battery --- p.7Chapter 2.2.2 --- Standardization of neurobehavioral test battery --- p.8Chapter 2.2.3 --- Reliability and validity --- p.9Chapter 2.2.4 --- Confounding factors of neurobehavioral test --- p.10Chapter 2.3 --- Neurobehavioral effects of different levels of solvent exposures --- p.12Chapter 2.3.1 --- Positive results in field studies --- p.12Chapter 2.3.2 --- Negative results in field studies --- p.17Chapter 2.3.3 --- Dose-response relationship in the field studies --- p.18Chapter 2.3.4 --- To separate acute and chronic effects --- p.20Chapter 2.3.5 --- The long-term effects of solvent exposure --- p.21Chapter 2.4 --- Limitations of these studies --- p.23Chapter 2.5 --- Summary --- p.26Chapter Chapter 3 --- Aims and Objectives --- p.31Chapter 3.1 --- Aims of the present research --- p.31Chapter 3.2 --- Position of this study cm this research domain --- p.32Chapter Chapter 4 --- Subjects and Method --- p.33Chapter 4.1 --- Study design --- p.33Chapter 4.2 --- Study population and sampling --- p.33Chapter 4.2.1 --- Participation --- p.33Chapter 4.2.2 --- Exposed group --- p.34Chapter 4.2.3 --- Reference group --- p.34Chapter 4.2.4 --- Sample size estimation --- p.34Chapter 4.3 --- Data collection --- p.36Chapter 4.3.1 --- Exposure assessment --- p.36Chapter 4.3.1.1 --- Air sample measurements --- p.36Chapter 4.3.1.2 --- Biological monitoring --- p.38Chapter 4.3.2. --- Medical assessment --- p.38Chapter 4.3.2.1 --- Pre-test questionnaire --- p.39Chapter 4.3.2.2 --- Neurobehavioral assessment --- p.39Chapter 4.4 --- Data Analysis --- p.43Chapter 4.4.1 --- Data Processing --- p.43Chapter 4.4.2 --- Statistical analysis --- p.44Chapter 4.4.2.1 --- Descriptive analysis --- p.44Chapter 4.4.2.2 --- Identifying the main confounding factories --- p.44Chapter 4.4.2.3 --- Comparing the tests score adjusted for confounding --- p.45Chapter 4.4.2.4 --- Dose-response analysis --- p.45Chapter Chapter 5 --- Results --- p.47Chapter 5.1 --- Demographic characteristics of the subjects --- p.47Chapter 5.2 --- Comparison of the basic characteristics between the exposed group and the reference group --- p.48Chapter 5.3 --- Comparison of the symptoms between the exposed group and the reference group --- p.49Chapter 5.4 --- Comparison of the scores of neurobehavioral tests between the exposed group and the reference group --- p.51Chapter 5.5 --- Identifying potential confounding of neurobehavioral test --- p.51Chapter 5.5.1 --- Main confounding factors of NCTB test on performance tests --- p.51Chapter 5.5.2 --- Main confounding factors of Profile of Mood States --- p.54Chapter 5.6 --- Groups comparison of the neurobehavioral effects --- p.57Chapter 5.6.1 --- Comparison of the adjusted mean scores between the exposed group and the reference group --- p.57Chapter 5.6.2 --- Groups comparison of the adjusted tests score in Factories C and G respectively --- p.58Chapter 5.7 --- Exposure assessment --- p.61Chapter 5.7.1 --- Air sampling results of the printing factories --- p.62Chapter 5.7.2 --- Relationship between results of active and passive sampling systems --- p.63Chapter 5.7.3 --- Biological monitoring --- p.63Chapter 5.8 --- Dose-response relationship --- p.65Chapter Chapter 6 --- Discussion --- p.69Chapter 6.1 --- Findings of this study --- p.69Chapter 6.1.1 --- Subjective symptoms --- p.69Chapter 6.1.2 --- Neurobehavioral effects --- p.70Chapter 6.1.3 --- Exposure intensity --- p.72Chapter 6.1.4. --- Dose-response relationship --- p.75Chapter 6.2 --- Applications of the study results --- p.76Chapter 6.2.1 --- The need for prevention measures --- p.77Chapter 6.2.2 --- Contributing to re-setting of OELs --- p.77Chapter 6.2.3. --- The evidence on neurotoxicology --- p.78Chapter 6.3 --- Limitations of the study --- p.79Chapter 6.3.1. --- Possibility of bias --- p.79Chapter 6.3.2. --- Lack of historical hygiene measurement data --- p.80Chapter 6.3.3. --- Influence of workshift --- p.81Chapter 6.3.4. --- Combined exposures to noise and organic solvents --- p.82Chapter 6.4 --- Conclusion --- p.83Appendices --- p.84Appendix 1 --- p.84Appendix 2 --- p.97Appendix 3 --- p.102Appendix 4 --- p.103Appendix 5 The Administration of The WHO-NCTB Tests --- p.114Test 1 Profile of Mood States Test --- p.115Test 2. Simple Reaction Time Test --- p.116Test 3. Digit Span Test Test --- p.119Test 4. Santa Ana Test --- p.120Test 5. Digit Symbol Test --- p.122Test 6. Benton Visual Retention Test --- p.123Test 7. Pursuit Aiming Test --- p.125Appendix 6 --- p.126Reference List --- p.12