317 research outputs found

    Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

    Get PDF
    The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: ‱ The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. ‱ Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. ‱ NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. ‱ Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

    S-RLNC based MAC Optimization for Multimedia Data Transmission over LTE/LTE-A Network

    Get PDF
    The high pace emergence in communication systems and associated demands has triggered academia-industries to achieve more efficient solution for Quality of Service (QoS) delivery for which recently introduced Long Term Evolution (LTE) or LTE-Advanced has been found as a promising solution. However, enabling QoS and Quality of Experience (QoE) delivery for multimedia data over LTE has always been a challenging task. QoS demands require reliable data transmission with minimum signalling overheads, computational complexity, minimum latency etc, for which classical Hybrid Automatic Repeat Request (HREQ) based LTE-MAC is not sufficient. To alleviate these issues, in this paper a novel and robust Multiple Generation Mixing (MGM) assisted Systematic Random Linear Network Coding (S-RLNC) model is developed to be used at the top of LTE MAC protocol stack for multimedia data transmission over LTE/LTE-A system. Our proposed model incorporated interleaving and coding approach along with MGM to ensure secure, resource efficient and reliable multiple data delivery over LTE systems. The simulation results reveal that our proposed S-RLNC-MGM based MAC can ensure QoS/QoE delivery over LTE systems for multimedia data communication

    Subcarrier and Power Allocation in WiMAX

    Get PDF
    Worldwide Interoperability for Microwave Access (WiMAX) is one of the latest technologies for providing Broadband Wireless Access (BWA) in a metropolitan area. The use of orthogonal frequency division multiplexing (OFDM) transmissions has been proposed in WiMAX to mitigate the complications which are associated with frequency selective channels. In addition, the multiple access is achieved by using orthogonal frequency division multiple access (OFDMA) scheme which has several advantages such as flexible resource allocation, relatively simple transceivers, and high spectrum efficient. In OFDMA the controllable resources are the subcarriers and the allocated power per subband. Moreover, adaptive subcarrier and power allocation techniques have been selected to exploit the natural multiuser diversity. This leads to an improvement of the performance by assigning the proper subcarriers to the user according to their channel quality and the power is allocated based on water-filling algorithm. One simple method is to allocate subcarriers and powers equally likely between all users. It is well known that this method reduces the spectral efficiency of the system, hence, it is not preferred unless in some applications. In order to handle the spectral efficiency problem, in this thesis we discuss three novel resources allocation algorithms for the downlink of a multiuser OFDM system and analyze the algorithm performances based on capacity and fairness measurement. Our intensive simulations validate the algorithm performances.fi=OpinnÀytetyö kokotekstinÀ PDF-muodossa.|en=Thesis fulltext in PDF format.|sv=LÀrdomsprov tillgÀngligt som fulltext i PDF-format

    Header Compression and Signal Processing for Wideband Communication Systems.

    Get PDF
    This thesis is dedicated to the investigation, development and practical verification of header compression and signal processing techniques over TErrestrial Trunked RAdio (TETRA), TETRA Enhanced Data Services (TEDS) and Power Line Communication (PLC). TETRA release I is a narrowband private mobile radio technology used by safety and security organizations, while TEDS is a widebandsystem. With the introduction of IP support, TEDS enables multimedia based applications and services to communicate across communication systems. However the IP extension for TEDS comes at a cost of significant header contributions with the payload. With small application payloads and fast rate application traffic profiles, the header contribution in the total size of the packet is considerably more than the actual application payload. This overhead constitutes the considerable slot capacity at the physical layer of TEDS and PLC. Advanced header compression techniques such as Robust Header Compression (RoHC) compress the huge header sizes and offer significant compression gain without compromising quality of service (QoS). Systems can utilize this bandwidth to transmit more information payload than control information. In this study, the objective is to investigate the integration of RoHC in TEDS and design a novel IPv6 enabled protocol stack for PLC with integrated RoHC. The purpose of the study is also to investigate the throughput optimization technique such as RoHC over TEDS and PLC by simulating different traffic profile classes and to illustrate the benefit of using RoHC over TEDS and PLC. The thesis also aims to design and simulate the TEDS physical layer for the purpose of investigating the performance of higher order modulation schemes. Current TEDS, standards are based on the transmission frequencies above 400MHz range, however with delays in the standardization of broadband TETRA, it is important to explore all possible avenues to extend the capacity of the system. The research concludes the finding of the application of RoHC for TEDS and PLC, against different traffic classes and propagation channels. The benefit of using RoHC in terms of saving bandwidth, slot capacity and other QoS parameters is presented along with integration aspects into TEDS and PLC communication stacks. The study also presents the TEDS physical layer simulation results for modulation schemes and transmission frequency other than specified in the standard. The research results presented in this thesis have been published in international symposiums and professional journals. The application of the benefits of using RoHC for TEDS has been proposed to the ETSI TETRA for contribution to the TETRA standard under STF 378. Simulation results for the investigation of characteristics of ?/4 DQPSK performance below 200 MHz have also been also presented to ETSI TETRA as a contribution to the existing TEDS standard. The Results presented for the design of IPv6 enabled stacked with integrated RoHC have been submitted as deliverable under the FP-7 project DLC+VIT4IP. All the results, simulations and investigations presented in the thesis have been carried out through the platform provided by HW Communication Ltd
    • 

    corecore