Design of low-dropout regulator for ultra low power on-chip applications

Low Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture

CMOS Design of Reconfigurable SoC Systems for Impedance Sensor Devices

La rápida evolución en el campo de los sensores inteligentes, junto con los avances en las tecnologías de la computación y la comunicación, está revolucionando la forma en que recopilamos y analizamos datos del mundo físico para tomar decisiones, facilitando nuevas soluciones que desempeñan tareas que antes eran inconcebibles de lograr.La inclusión en un mismo dado de silicio de todos los elementos necesarios para un proceso de monitorización y actuación ha sido posible gracias a los avances en micro (y nano) electrónica. Al mismo tiempo, la evolución de las tecnologías de procesamiento y micromecanizado de superficies de silicio y otros materiales complementarios ha dado lugar al desarrollo de sensores integrados compatibles con CMOS, lo que permite la implementación de matrices de sensores de alta densidad. Así, la combinación de un sistema de adquisición basado en sensores on-Chip, junto con un microprocesador como núcleo digital donde se puede ejecutar la digitalización de señales, el procesamiento y la comunicación de datos proporciona características adicionales como reducción del coste, compacidad, portabilidad, alimentación por batería, facilidad de uso e intercambio inteligente de datos, aumentando su potencial número de aplicaciones.Esta tesis pretende profundizar en el diseño de un sistema portátil de medición de espectroscopía de impedancia de baja potencia operado por batería, basado en tecnologías microelectrónicas CMOS, que pueda integrarse con el sensor, proporcionando una implementación paralelizable sin incrementar significativamente el tamaño o el consumo, pero manteniendo las principales características de fiabilidad y sensibilidad de un instrumento de laboratorio. Esto requiere el diseño tanto de la etapa de gestión de la energía como de las diferentes celdas que conforman la interfaz, que habrán de satisfacer los requisitos de un alto rendimiento a la par que las exigentes restricciones de tamaño mínimo y bajo consumo requeridas en la monitorización portátil, características que son aún más críticas al considerar la tendencia actual hacia matrices de sensores.A nivel de celdas, se proponen diferentes circuitos en un proceso CMOS de 180 nm: un regulador de baja caída de voltaje como unidad de gestión de energía, que proporciona una alimentación de 1.8 V estable, de bajo ruido, precisa e independiente de la carga para todo el sistema; amplificadores de instrumentación con una aproximación completamente diferencial, que incluyen una etapa de entrada de voltaje/corriente configurable, ganancia programable y ancho de banda ajustable, tanto en la frecuencia de corte baja como alta; un multiplicador para conformar la demodulación dual, que está embebido en el amplificador para optimizar consumo y área; y filtros pasa baja totalmente integrados, que actúan como extractores de magnitud de DC, con frecuencias de corte ajustables desde sub-Hz hasta cientos de Hz.<br /

A New Design Methodology For Enhancing The Transient Loading Of Low Drop-out Regulators (LDRs)

A new simple design methodology which makes LDR output nearly insensitive to jumps of the load current for long times is proposed. This methodology is tested for more than 104 seconds. Our procedure leans on cross coupling of the time second derivative of the LDR power transistor gate and drain voltages along with their currents. This technique keeps low values of these currents in order of nano or hundreds of micro amperes for undershot or overshot cases, respectively. The introduced methodology has been applied to a standard CMOS of 0.18μm technology for NMOS transistors and validated using MATLAB R2014a

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

CMOS analog integrated circuit design techniques for low-powered ubiquitous device

制度:新 ; 文部省報告番号:甲2633号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新479

Integrated circuit & system design for concurrent amperometric and potentiometric wireless electrochemical sensing

Complementary Metal-Oxide-Semiconductor (CMOS) biosensor platforms have steadily grown in healthcare and commerial applications. This technology has shown potential in the field of commercial wearable technology, where CMOS sensors aid the development of miniaturised sensors for an improved cost of production and response time. The possibility of utilising wireless power and data transmission techniques for CMOS also allows for the monolithic integration of the communication, power and sensing onto a single chip, which greatly simplifies the post-processing and improves the efficiency of data collection. The ability to concurrently utilise potentiometry and amperometry as an electrochemical technique is explored in this thesis. Potentiometry and amperometry are two of the most common transduction mechanisms for electrochemistry, with their own advantages and disadvantages. Concurrently applying both techniques will allow for real-time calibration of background pH and for improved accuracy of readings. To date, developing circuits for concurrently sensing potentiometry and amperometry has not been explored in the literature. This thesis investigates the possibility of utilising CMOS sensors for wireless potentiometric and amperometric electrochemical sensing. To start with, a review of potentiometry and amperometry is evaluated to understand the key factors behind their operation. A new configuration is proposed whereby the reference electrode for both electrochemistry techniques are shared. This configuration is then compared to both the original configurations to determine any differences in the sensing accuracy through a novel experiment that utilises hydrogen peroxide as a measurement analyte. The feasibility of the configuration with the shared reference electrode is proven and utilised as the basis of the electrochemical configuration for the front end circuits. A unique front-end circuit named DAPPER is developed for the shared reference electrode topology. A review of existing architectures for potentiometry and amperometry is evaluated, with a specific focus on low power consumption for wireless applications. In addition, both the electrochemical sensing outputs are mixed into a single output data channel for use with a near-field communication (NFC). This mixing technique is also further analysed in this thesis to understand the errors arising due to various factors. The system is fabricated on TSMC 180nm technology and consumes 28µW. It measures a linear input current range from 250pA - 0.1µW, and an input voltage range of 0.4V - 1V. This circuit is tested and verified for both electrical and electrochemical tests to showcase its feasibility for concurrent measurements. This thesis then provides the integration of wireless blocks into the system for wireless powering and data transmission. This is done through the design of a circuit named SPACEMAN that consists of the concurrent sensing front-end, wireless power blocks, data transmission, as well as a state machine that allows for the circuit to switch between modes: potentiometry only, amperometry only, concurrent sensing and none. The states are switched through re-booting the circuit. The core size of the electronics is 0.41mm² without the coil. The circuit’s wireless powering and data transmission is tested and verified through the use of an external transmitter and a connected printed circuit board (PCB) coil. Finally, the future direction for ongoing work to proceed towards a fully monolithic electrochemical technique is discussed through the next development of a fully integrated coil-on-CMOS system, on-chip electrodes with the electroplating and microfludics, the development of an external transmitter for powering the device and a test platform. The contributions of this thesis aim to formulate a use for wireless electrochemical sensors capable of concurrent measurements for use in wearable devices.Open Acces

Diseño de circuitos electrónicos de ultra-bajo consumo en tecnologías nanométricas

El escalado de los procesos de fabricación de semiconductores, predicho por el Dr. Moore en los años sesenta, ha tenido un gran impacto en el desarrollo de la electrónica integrada actual. Por una parte, la reducción del tamaño de los transistores ha permitido incrementar la densidad de integración, dando la posibilidad a los diseñadores de introducir un mayor número de funcionalidades dentro de una misma área. Por otro lado, este fenómeno ha llevado consigo una reducción de los costes asociados a la fabricación, logrando abaratar el producto final. Esta continua evolución e incremento de la funcionalidad dentro de un mismo circuito integrado, implica, a su vez, un aumento de la complejidad a la hora de planificar la generación y distribución de las distintas tensiones de alimentación, necesarias para cada uno de los bloques incluidos en el chip. Esto provoca que las especificaciones de ruido, regulación y/o estabilidad asociadas a cada dominio de alimentación varíen según la naturaleza del sistema al que se pretende alimentar. Por esta razón, los circuitos destinados a la gestión de la potencia han tomado una mayor relevancia en los últimos años, puesto que las restricciones impuestas por los sistemas integrados son cada vez mayores. Dentro de los circuitos destinados a la gestión de potencia, los reguladores lineales y, en concreto, los de bajo dropout se corresponden con un bloque básico, ya que permiten la generación de tensiones de alimentación muy estables, precisas y de bajo ruido. Estas características los convierten en el circuito ideal para alimentar a sistemas analógicos o de radio-frecuencia, muy sensibles a variaciones de la alimentación. Otra característica de estos bloques, que ha provocado el creciente interés de la comunidad científica en ellos, es la posibilidad de poder integrarlos sin necesidad de incluir ningún dispositivo externo, con el consecuente ahorro económico y de área en la tarjeta impresa. Sin embargo, dentro de los inconvenientes cabe destacar dos. Por una parte, la eficiencia máxima teórica que pueden lograr es baja frente a soluciones basadas en capacidades conmutadas o inductores. Por otro lado, al buscarse un esquema de compensación interna, el polo dominante del sistema viene fijado por un nodo interno del circuito, provocando que el polo no-dominante esté dominado por la carga. Esto se traduce en un gran problema de estabilidad, debido a que las variaciones que sufre la carga se traducen en un desplazamiento en frecuencia del polo no dominante, degradando el margen de fase de todo el sistema. Según lo descrito anteriormente, esta investigación se ha centrado en el estudio de reguladores lineales de tipo Low-DropOut o LDO compensados internamente y sus propiedades, dada la problemática de este tipo de celdas cuando se busca minimizar su consumo quiescente. Para ello, uno de los objetivos marcados versa sobre la búsqueda de topologías alternativas que permitan el diseño de LDOs de altas prestaciones, sin suponer un incremento del consumo quiescente y que sean válidos para entornos de baja tensión de alimentación. En este sentido, se ha apostado por el uso de la celda Flipped Voltage Follower como regulador debido a su baja impendancia de salida, gran estabilidad y sencillez. Una segunda línea, se ha centrado en la búsqueda de esquemas de compensación simples que permitan extender la estabilidad de este tipo de regulador en todo el rango de funcionamiento. Para ello, se ha explorado un esquema basado en la compensación clásica de Miller donde se ha utilizado un esquema de replica para ajustar de forma dinámica el valor de la resistencia según la carga del sistema. Por último, con el objetivo de minimizar lo máximo posible el consumo quiescente de los reguladores LDOs sin degradar las prestaciones de la respuesta transitoria, se ha explorado el uso de buffers clase AB para gestionar la puerta del transistor de paso. Esta técnica permite mejorar la respuesta transitoria, al ser capaz de crear corrientes elevadas durante las transiciones sin necesidad de penalizar la eficiencia del regulador.The continuous downscaling of semiconductor fabrication processes, which was predicted by PhD. Moore in 1965, have had a great impact in the development of nowadays integrated electronics. The reduction of transistor size has allowed, on one hand, the integration of more devices in the same área, increasing the integration density, while, on the other hand, has led to the reduction of fabrication costs, making the final product cheaper and accessible. However, this increase in the functionality of a single integrated circuit entails greater complexity in the generation and distribution of the different biasing voltages needed throughout one chip. Thus, as more different systems are integrated in the same chip, more different biasing domains coexists in it, leading several different requirements of noise, regulation and/or stability that need to be satisfied simultaneously. Therefore, power management circuits have been acquiring greater significance as technology downscales, reaching its maximum nowadays, when the nanoscale had taken those issues to its culmen. Linear regulators, and more concretely, low-dropout linear regulators, are an essential block in any power management system, able to generate precise and extremely-stable low-noise biasing voltages what make them the ideal choice for extremely biasing-sensitive circuits such as analog or radio-frequency systems. In addition to this, low-dropout linear regulators can be completely integrated without needing any external device, what translates to expenses and area savings. For all these reasons, low-dropout linear regulators have been lately acquiring extensive attention from the scientific community. However, those circuits also have some disadvantages, indeed, the maximum theoretical efficiency that can be achieved though low-dropout linear regulators is lower than switched capacitor or inductor-based solutions efficiency. In addition to this, as internal compensation is required, the system’s dominant pole is given by an internal node, making the non-dominant pole to be fixed by the charge. This leads to a great stability concern as charge variations translate to a frequency displacement of the non-dominant pole that degrades the whole system phase margin. In accordance with previously described issues, this research has been focused on the study of minimum-quiescent consumption internally compensated low-dropout linear regulators (LDO). The first objective of this research is the proposal of low-voltage high-performance LDO structures that do not increase quiescent consumption. Thus, the Flipped Voltage Follower cell has been proposed as regulator due to its inherent low output impedance, great stability and simplicity. The second aim of this research has been the proposal of simple compensation schemes that allow full-operation range stability. So that, a classical Miller compensation based scheme where a replica circuit dynamically adjust the charge resistance has been proposed. Finally, in order to minimize quiescent consumption of LDOs regulators without degrading transient response performance, class-AB buffers have been proposed to drive the pass transistor gate. This technique enhances the transient response as it generates high currents during transitions without compromising efficiency.Premio Extraordinario de Doctorado U

Design of Analog & Mixed Signal Circuits in Continuous-Time Sigma-Delta Modulators for System-on-Chip applications

Software-defined radio receivers (SDRs) have become popular to accommodate multi-standard wireless services using a single chip-set solution in mobile telecommunication systems. In SDRs, the signal is down-converted to an intermediate frequency and then digitalized. This approach relaxes the specifications for most of the analog front-end building blocks by performing most of the signal processing in the digital domain. However, since the analog-to-digital converter (ADC) is located as close as possible to the antenna in SDR architectures, the ADC specification requirements are very stringent because a large amount of interference signals are present at the ADC input due to the removal of filtering blocks, which particularly affects the dynamic range (DR) specification. Sigma-delta (ΣΔ) ADCs have several benefits such as low implementation cost, especially when the architecture contains mostly digital circuits. Furthermore, continuous-time (CT) ΣΔ ADCs allow elimination of the anti‐aliasing filter because input signals are sampled after the integrator. The bandwidth requirements for the amplifiers in CT ΣΔ ADCs can be relaxed due to the continuous operation without stringing settling time requirements. Therefore, they are suitable for high‐speed and low‐power applications. In addition, CT ΣΔ ADCs achieve high resolution due to the ΣΔ modulator’s noise shaping property. However, the in-band quantization noise is shaped by the analog loop filter and the distortions of the analog loop filter directly affect the system output. Hence, highly linear low-noise loop filters are required for high-performance ΣΔ modulators. The first task in this research focused on using CMOS 90 nm technology to design and fabricate a 5^(TH)–order active-RC loop filter with a cutoff frequency of 20 MHz for a low pass (LP) CT ΣΔ modulator. The active-RC topology was selected because of the high DR requirement in SDR applications. The amplifiers in the first stage of the loop filter were implemented with linearization techniques employing anti-parallel cancellation and source degeneration in the second stage of the amplifiers. These techniques improve the third-order intermodulation (IM3) by approximately 10 dB; while noise, area, and power consumption do not increase by more than 10%. Second, a current-mode adder-flash ADC was also fabricated as part of a LP CT ΣΔ modulator. The new current-mode operation developed through this research makes possible a 53% power reduction. The new technology also lessens existing problems associated with voltage-mode flash ADCs, which are mainly related to voltage headroom restrictions, speed of operation, offsets, and power efficiency of the latches. The core of the current-mode adder-flash ADC was fabricated in CMOS 90 nm technology with 1.2 V supply; it dissipates 3.34 mW while operating at 1.48 GHz and consumes a die area of 0.0276 mm^(2). System-on chip (SoC) solutions are becoming more popular in mobile telecommunication systems to improve the portability and competitiveness of products. Since the analog/RF and digital blocks often share the same external power supply in SoC solutions, the on-chip generation of clean power supplies is necessary to avoid system performance degradation due to supply noises. Finally, the critical design issues for external capacitor-less low drop-out (LDO) regulators for SoC applications are addressed in this dissertation, especially the challenges related to power supply rejection at high frequencies as well as loop stability and transient response. The paths of the power supply noise to the LDO output were analyzed, and a power supply noise cancellation circuit was developed. The power supply rejection (PSR) performance was improved by using a replica circuit that tracks the main supply noise under process-voltage-temperature variations and all operating conditions. Fabricated in a 0.18 μm CMOS technology with 1.8 V supply, the entire proposed LDO consumes 55 μA of quiescent current while in standby operation, and it has a drop-out voltage of 200 mV when providing 50 mA to the load. Its active core chip area is 0.14 mm2. Compared to a conventional uncompensated LDO, the proposed architecture presents a PSR improvement of 34 dB and 25 dB at 1 MHz and 4 MHz, respectively