Ultra-Low Power Circuit Design for Miniaturized IoT Platform

This thesis examines the ultra-low power circuit techniques for mm-scale Internet of Things (IoT) platforms. The IoT devices are known for their small form factors and limited battery capacity and lifespan. So, ultra-low power consumption of always-on blocks is required for the IoT devices that adopt aggressive duty-cycling for high power efficiency and long lifespan. Several problems need to be addressed regarding IoT device designs, such as ultra-low power circuit design techniques for sleep mode and energy-efficient and fast data rate transmission for active mode communication. Therefore, this thesis highlights the ultra-low power always-on systems, focusing on energy efficient optical transmission in order to miniaturize the IoT systems. First, this thesis presents a battery-less sub-nW micro-controller for an always-operating system implemented with a newly proposed logic family. Second, it proposes an always-operating sub-nW light-to-digital converter to measure instant light intensity and cumulative light exposure, which employs the characteristics of this proposed logic family. Third, it presents an ultra-low standby power optical wake-up receiver with ambient light canceling using dual-mode operation. Finally, an energy-efficient low power optical transmitter for an implantable IoT device is suggested. Implications for future research are also provided.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/145862/1/imhotep_1.pd

Ultra-Low Power Circuit Design for Cubic-Millimeter Wireless Sensor Platform.

Modern daily life is surrounded by smaller and smaller computing devices. As Bell’s Law predicts, the research community is now looking at tiny computing platforms and mm3-scale sensor systems are drawing an increasing amount of attention since they can create a whole new computing environment. Designing mm3-scale sensor nodes raises various circuit and system level challenges and we have addressed and proposed novel solutions for many of these challenges to create the first complete 1.0mm3 sensor system including a commercial microprocessor. We demonstrate a 1.0mm3 form factor sensor whose modular die-stacked structure allows maximum volume utilization. Low power I2C communication enables inter-layer serial communication without losing compatibility to standard I2C communication protocol. A dual microprocessor enables concurrent computation for the sensor node control and measurement data processing. A multi-modal power management unit allowed energy harvesting from various harvesting sources. An optical communication scheme is provided for initial programming, synchronization and re-programming after recovery from battery discharge. Standby power reduction techniques are investigated and a super cut-off power gating scheme with an ultra-low power charge pump reduces the standby power of logic circuits by 2-19× and memory by 30%. Different approaches for designing low-power memory for mm3-scale sensor nodes are also presented in this work. A dual threshold voltage gain cell eDRAM design achieves the lowest eDRAM retention power and a 7T SRAM design based on hetero-junction tunneling transistors reduces the standby power of SRAM by 9-19× with only 15% area overhead. We have paid special attention to the timer for the mm3-scale sensor systems and propose a multi-stage gate-leakage-based timer to limit the standard deviation of the error in hourly measurement to 196ms and a temperature compensation scheme reduces temperature dependency to 31ppm/°C. These techniques for designing ultra-low power circuits for a mm3-scale sensor enable implementation of a 1.0mm3 sensor node, which can be used as a skeleton for future micro-sensor systems in variety of applications. These microsystems imply the continuation of the Bell’s Law, which also predicts the massive deployment of mm3-scale computing systems and emergence of even smaller and more powerful computing systems in the near future.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91438/1/sori_1.pd

Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

Investigation of the power-clock network impact on adiabatic logic

International audienceAdiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency

Design And Analysis of 1-Bit Full Adder and Logic Gates

The scaling of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) are commonly used in high speed integrated circuits, yield smaller and faster more functions at lower cost. Various problems exist with scaling of MOSFET devices i.e. short channel effects (SCE), drain induced barrier lowering, velocity saturation which limits the performance of MOSFETs. Scaling limitations of MOSFET devices leads to lower ON to OFF current ratio limited by 60mV/dec sub threshold slope.A new type of device called “Tunnel FET” is used to overcome these difficulties. TFET can beat 60mV/dec sub-threshold swing of MOSFETs. In Tunnel FET the carrier are generated by band-to-band tunneling and OFF current is low. Tunnel FET have energy barrier in OFF state, which avoids application where leakage is concern of interest. In this Project sub-threshold swing and low OFF current is simulated and its power is analyzed.Basically in VLSI circuit like design of IC we have to simulate all the parameters of the devices & circuit regarding of that IC or any devices like FET, MOSFET, CMOS etc. In device simulation we are most widely use software named as “HSPICE”. We are doing analysis of full bit adder. We are going to compare different characteristics

Therapeutic capsule endoscopy: Opportunities and challenges

10.1260/2040-2295.2.4.459Journal of Healthcare Engineering24459-47

Power Management Techniques for Micropower Energy Scavenging

Advances in semi-conductor technology have led to the reduction in size and power consumption of microelectronic circuits. With the miniaturization and increased efficiency of these circuits there are more potential applications for wireless sensor networks and portable electronic equipment. These applications include structural integrity and environment monitoring such as aircraft wing health monitoring and forest fire and natural disaster detection. Biomedical devices have also benefited from the improved size and performance of microelectronics. This thesis studies power management techniques to enable efficient energy scavenging at micropower input power levels from a number of power sources. These sources range from temperature gradients, radio frequency (RF) radiation, solar power, and mechanical vibrations. The scavenged energy is used to improve the performance and distribution of wireless sensors and devices by supplementing or potentially replacing the local power supply of the sensor or device. The major focus of this thesis is to combine source characterization, power management theory, detailed power loss analysis, and ultra-low power circuit design to maximize the extraction of energy from source and deliver it to the wireless sensor or device. The resistor emulation techniques from power factor correction (PFC) are leveraged to load an RF rectifying antenna (rectenna) such that maximum power point tracking (MPPT) of the rectenna is achieved naturally. An application specific integrated circuit (ASIC) is developed to implement this technique after experimental verification with commercially available discrete circuitry. Experimental results show efficient energy scavenging at power levels below 2 microwatts. In addition to resistor emulation, synchronous electric charge extraction (SECE) for energy scavenging from piezoelectric generators is also investigated. The presented techniques allow for the scavenging of usable power for sensors at power levels significantly lower than previous research

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 μ m CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 μ W. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD)

Therapeutic capsule endoscopy: Opportunities and challenges

ABSTRACT The increasing demand for non-invasive (or less-invasive) monitoring and treatment of medical conditions has attracted both physicians and engineers to work together and investigate new methodologies. Wireless capsule endoscopy is a successful example of such techniques which has become an accepted routine for diagnostic inspection of the gastrointestinal tract. This method offers a non-invasive alternative to traditional endoscopy and provides the opportunity for exploring distal areas of the small intestine which are otherwise not accessible. Despite these advantages, wireless capsule endoscopy is still limited in functionality compared to traditional endoscopy. Wireless capsule endoscopes with advanced functionalities, such as biopsy or drug delivery, are highly desirable. In this article, the current status of wireless capsule endoscopy is reviewed together with some of its possible therapeutic applications as well as the existing challenges