51 research outputs found
Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology
La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic
Wireless wire - ultra-low-power and high-data-rate wireless communication systems
With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day
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Recursive receiver down-converters with multiband feedback and gain-reuse for low-power applications
Power minimization in wireless transceivers has become increasingly critical in recent years with the emergence of standards for short-distance applications in the 900 MHz and 2.4 GHz industrial, scientific and medical (ISM) radio bands. The demand for long battery life and better portability in such applications has led to extensive research on low power radio architectures. This dissertation introduces receiver topologies for low-power systems and presents a theoretical performance analysis of the topologies. Two fully integrated receiver down-converters that demonstrate the concept are implemented in a 0.13-[mu]m CMOS technology. These topologies employ merged mixers and IF amplifiers in order to reduce power dissipation for a given dynamic range performance. In the described topologies, the input stage of a mixer is used to simultaneously provide conversion gain and baseband amplification. This is achieved by applying the down-converted IF signal to input of the mixer. Consequently, the effective conversion gain of the design is greatly enhanced with current requirement primarily determined by the input transconductor. Potential degradation mechanisms related to instability and second-order distortion are identified and solved by the use of appropriate circuit techniques. Noise and linearity performance of the down-converters is analyzed and compared to that of conventional cascaded design counterparts. The potential for enhancement of IIP3 performance through cancellation of nonlinear products is discussed. Potential extensions of the above work including feedback-based architectures that exploit multiple loops for further maximizing the power efficiency of receiver front-ends are also presented.Electrical and Computer Engineerin
Analysis and Design of Wideband Low Noise Amplifier with Digital Control
The design issues in designing low noise amplifier (LNA) for Software-Defined-Radio (SDR) are reviewed. An inductor-less wideband low noise amplifier aiming at low frequency band (0.2-2GHz) for Software-Defined-Radio is presented. Shunt-shunt LNA with active feedback is used as the first stage which is carefully optimized for low noise and wide band applications. A digitally controlled second stage is employed to provide an additional 12dB gain control. A novel method is proposed to bypass the first stage without degrading input matching. This LNA is fabricated in a standard 0.18 um CMOS technology. The measurement result shows the proposed LNA has a gain range of 6dB-18dB at high gain mode and -12dB-0dB at low gain mode, as well as a –3dB bandwidth of 2GHz. The noise figure (NF) is 3.5-4.5dB in the high gain setting mode. It consumes 20mW from a 1.8V supply
HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING
In future, the radar/satellite wireless communication devices must support multiple standards
and should be designed in the form of system-on-chip (SoC) so that a significant reduction
happen on cost, area, pins, and power etc. However, in such device, the design of a fully
on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously
becomes a multifold complex problem. Further, the inherent high-power out-of-band
(OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate
the receiver. Therefore, the proper blocker rejection techniques need to be incorporated.
The primary focus of this research work is the development of a CMOS high-performance low
noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further,
the various reconfigurable mixer architectures are proposed for performance adaptability of a
wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced
fully differential receiver is proposed. The receiver composed of a composite transistor
pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor
amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based
tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture
in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver
system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides
a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB
having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured
receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm,
occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary
subthreshold receiver is proposed to estimate the out of blocker power. As a redundant
block in the system, the cost and power minimization of the auxiliary receiver are achieved
via subthreshold circuit design techniques and implementing the design in higher technology
node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the
noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power
consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver
and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various
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reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance
according to the requirement of the selected communication standard. The down conversion mixers
configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth
reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept,
the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured
result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of
-11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW
and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz
for active/passive case respectively
Energy-Efficient Wireless Circuits and Systems for Internet of Things
As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications.
This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd
High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications
The prevalence of wireless standards and the introduction of dynamic
standards/applications, such as software-defined radio, necessitate the next generation
wireless devices that integrate multiple standards in a single chip-set to support a variety
of services. To reduce the cost and area of such multi-standard handheld devices,
reconfigurability is desirable, and the hardware should be shared/reused as much as
possible. This research proposes several novel circuit topologies that can meet various
specifications with minimum cost, which are suited for multi-standard applications. This
doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the
RF front-end; and 2. The analog-to-digital converter (ADC).
The first part of this dissertation focuses on LNA noise reduction and linearization
techniques where two novel LNAs are designed, taped out, and measured. The first LNA,
implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm
CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an
inductor connected at the gate of the cascode transistor and the capacitive cross-coupling
to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and
voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power
consumption. The second LNA, implemented in UMC (United Microelectronics
Corporation) 0.13Cm CMOS process, features a practical linearization technique for
high-frequency wideband applications using an active nonlinear resistor, which obtains a
robust linearity improvement over process and temperature variations. The proposed
linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB
over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior
published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized
UWB LNA achieves excellent linearity with much less power than previously published
works.
The second part of this dissertation developed a reconfigurable ADC for multistandard
receiver and video processors. Typical ADCs are power optimized for only one
operating speed, while a reconfigurable ADC can scale its power at different speeds,
enabling minimal power consumption over a broad range of sampling rates. A novel
ADC architecture is proposed for programming the sampling rate with constant biasing
current and single clock. The ADC was designed and fabricated using UMC 90nm
CMOS process and featured good power scalability and simplified system design. The
programmable speed range covers all the video formats and most of the wireless
communication standards, while achieving comparable Figure-of-Merit with customized
ADCs at each performance node. Since bias current is kept constant, the reconfigurable
ADC is more robust and reliable than the previous published works
Simulations of III-V NWFET Double-Balanced Gilbert Cells with an Improved Noise Model
III-V nanowire transistors might provide a mean for extending Moore’s law, by overcoming the scaling limitations ultimately facing planar silicon CMOS. These high frequency capable transistors with cut-off frequencies in the terahertz regime are suitable for radio communication. In this project an active double-balanced gilbert cell mixer consisting of nanowire field-effect transistors (NWFETs) was simulated in Cadence Virtuoso using a compact transistor model. The transistor model was extended to take flicker and thermal noise into account, in order to more accurately compare the mixers against state-of-the-art silicon CMOS implementations. The final mixer for 60 GHz showed much greater linearity (0.4 dBm 1 dB compression and 8.5 dBm IIP 3) than previously reported silicon CMOS counterparts. It exhibited a conversion gain of 3.47 dB, a N F DSB of 14.6 dB and a DC power consumption of 8.7 mW.Based on these findings the design requirements for suitable low noise amplifier was discussed
Energy Aware RF Transceiver for Wireless Body Area Networks (WBAN)
Ph.DDOCTOR OF PHILOSOPH
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