Electronics Emulation for Real-Time Fault Location in Power Systems

This research presents a high-speed hardware platform dedicated to emulate electrical power networks for the fault location. The solution implements an algorithm based on the Electromagnetic Time-Reversal (EMTR) principle, which allows locating faults in various network types and topologies. Although the technique is highly robust and accurate, its processing is complex and time consuming if solved with classical digital approaches. Therefore, a dedicated computation platform optimized on the processing speed was developed in order to allow its real-time implementation and make it compatible with smart-grids. Two different power network modelling approaches are presented. The first one is based on a finite element representation of the distributed parameters transmission line. The lossless line, initially characterized by a per-unit length inductance and capacitance, is replaced by a series of identical ladder connected inductor-capacitor (LC) elements. The second model is based on the general solution of the telegrapher's equations describing the signals propagated along the transmission line. In this method, the travelling waves' propagation taking place in the line is simulated with cascaded discrete-time delay elements. A possible implementation by means of analog circuits is then presented for each line model. The discretized parameters LC line is simulated by transconductance-capacitor, also called gyrator-C or gm-C topologies, more suitable for microelectronic implementation. On the other hand, the discrete-time delay element of the second method is implemented by switched-capacitor (SC) circuits. The processing time associated to each method can be scaled down according to the microelectronic parameters of the LC line, or by increasing the sampling frequency of the discrete-time model. Through this time scaling, the hardware emulation allows a fault location within duration of up to a hundred times shorter than with classical digital implementations of similar accuracy. The impact of non-ideal effects associated to the microelectronic implementation, such as the CMOS active elements finite gain, offset and dynamic range, or the switched-capacitor charge injection, etc., is evaluated for each model. Associated design constraints are then derived in order to ensure a given fault location accuracy, similarly to that of classical digital methods. Since the switched-capacitor model is characterized by higher robustness and accuracy than the LC line, it is therefore preferred for a silicon implementation. Results obtained after a CMOS AMS 0.35um process implementation have shown that the discrete-time model allows a fault location within 160ms, versus 6s in a classical digital method, with similar resolution (1%). The speed improvement obtained through the presented method is essential, potentially allowing real-time fault management in power grids. Finally, the impact of the magnitude quantization on the line model, offering perspectives of full digital implementations, is evaluated. A possible extension of the model for the simulation of interconnected or multi-conductor lines is also discussed

Design and Control of Power Converters for High Power-Quality Interface with Utility and Aviation Grids

Power electronics as a subject integrating power devices, electric and electronic circuits, control, and thermal and mechanic design, requires not only knowledge and engineering insight for each subarea, but also understanding of interface issues when incorporating these different areas into high performance converter design.Addressing these fundamental questions, the dissertation studies design and control issues in three types of power converters applied in low-frequency high-power transmission, medium-frequency converter emulated grid, and high-frequency high-density aviation grid, respectively, with the focus on discovering, understanding, and mitigating interface issues to improve power quality and converter performance, and to reduce the noise emission.For hybrid ac/dc power transmission,• Analyze the interface transformer saturation issue between ac and dc power flow under line unbalances.• Proposed both passive transformer design and active hybrid-line-impedance-conditioner to suppress this issue.For transmission line emulator,• Propose general transmission line emulation schemes with extension capability.• Analyze and actively suppress the effects of sensing/sampling bias and PWM ripple on emulation considering interfaced grid impedance.• Analyze the stability issue caused by interaction of the emulator and its interfaced impedance. A criterion that determines the stability and impedance boundary of the emulator is proposed.For aircraft battery charger,• Investigate architectures for dual-input and dual-output battery charger, and a three-level integrated topology using GaN devices is proposed to achieve high density.• Identify and analyze the mechanisms and impacts of high switching frequency, di/dt, dv/dt on sensing and power quality control; mitigate solutions are proposed.• Model and compensate the distortion due to charging transition of device junction capacitances in three-level converters.• Find the previously overlooked device junction capacitance of the nonactive devices in three-level converters, and analyze the impacts on switching loss, device stress, and current distortion. A loss calculation method is proposed using the data from the conventional double pulse tester.• Establish fundamental knowledge on performance degradation of EMI filters. The impacts and mechanisms of both inductive and capacitive coupling on different filter structures are understood. Characterization methodology including measuring, modeling, and prediction of filter insertion loss is proposed. Mitigation solutions are proposed to reduce inter-component coupling and self-parasitics

Experimental Investigation and Evaluation of Future Active Distribution Networks

The UK government’s policy to achieve a 20% renewable energy generation target by 2020, will require significant amounts of SSEG (Small-Scale Embedded Generation) to be connected. In addition to the expected economic and environmental benefits, the anticipated growth in SSEG brings with it numerous challenges for the operation of low voltage and medium voltage distribution networks. At present, there are a number of competing active network management concepts being considered to overcome these challenges and at Durham University a concept defined as the Small Scale Energy Zone (SSEZ) has been proposed and is investigated as part of this research. To further this, a bespoke active low voltage distribution network emulator known as the Experimental SSEZ has been developed by the author. Controllable emulated SSEG, controllable energy storage and controllable emulated load are incorporated into this laboratory. A transformation system has been developed to relate the operation of this system to that of low voltage distribution networks. Centralised and distributed network control systems have been developed for the Experimental SSEZ. These systems were used to evaluate, in conjunction with the relevant literature, the implementation of similar systems on future low voltage distribution networks. Both centralised and distributed control system architectures were found to have their merits. This research should therefore be useful in informing design decisions when developing and implementing active distribution network management systems on LV networks

A survey of emerging architectural techniques for improving cache energy consumption

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students

Multi Agent Systems for the Active Management of Electrical Distribution Networks

This Thesis presents an investigation on the technical impacts caused by the steady state operation of Small-Scale Embedded Generators (SSEGs) and also introduces the Small Scale Energy Zone (SSEZ) concept which aims to remove the technical barriers associated with SSEGs through intelligent coordination of large numbers of customerowned SSEGs, energy storage units and controllable loads. This approach represents a move away from the conventional passive, “fit-and-forget” philosophy under which the majority of Low Voltage (LV) distribution networks are currently operated and towards a higher degree of network operational management. The employment of a distributed management and control approach for an SSEZ, realised through the Multi Agent Systems (MAS) technology, is proposed due to the advantages that can potentially be realised in the areas of: (i) scalability and openness, (ii) reliability and resilience and (iii) communications efficiency. A FIPA-compliant MAS-based control approach is designed, developed and evaluated based on the specific SSEZ control requirements. The MAS is composed of three types of agents: direct control agents, indirect control agents and utility agents, exchanging information through the employment of a common ontology. In addition, a relational database management system is also designed and developed in order to be coupled with the developed MAS for data management purposes

Grid-Connected Renewable Energy Sources

The use of renewable energy sources (RESs) is a need of global society. This editorial, and its associated Special Issue “Grid-Connected Renewable Energy Sources”, offers a compilation of some of the recent advances in the analysis of current power systems that are composed after the high penetration of distributed generation (DG) with different RESs. The focus is on both new control configurations and on novel methodologies for the optimal placement and sizing of DG. The eleven accepted papers certainly provide a good contribution to control deployments and methodologies for the allocation and sizing of DG

Overcoming electro-thermal barriers to achieve extreme performance power conversion for more electric aircraft

The National Aeronautics and Space Administration (NASA), in addition to an increasing number of privately funded ventures, has demonstrated growing interest in more electric aircraft (MEA) - flight vehicles where propulsion is partially or totally supplied by electric motors. While hybrid or turbo-electric MEA concepts would still rely on a jet engine power plant to provide electrical power to these electric motors, NASA studies indicate these concepts can result in cleaner, quieter, and more fuel-efficient flight compared to current best-in-class passenger jet aircraft. To achieve this new paradigm in flight, major engineering challenges must be overcome to improve the thermal management, efficiency and power density of the propulsion electronics as well as ensure the high reliability necessary for aviation. This thesis focuses on these challenges in the scope of one block of this electrical system: a high-performance dc-ac converter designed to drive the type of electric machine engineered for electric flight from a high-voltage dc bus that would be present on some MEA concepts. The flying capacitor multilevel topology is demonstrated as an enabling technology for simultaneously achieving high-efficiency and high power-density, with specific consideration given to packaging and implementation. Reliability of the converter is addressed through discussion of on-line health management through the use of a real-time hardware-in-the-loop (HIL) observer

Fast Simulation of Electromagnetic Transients in Power Systems:Numerical Solvers and their Coupling with the Electromagnetic Time Reversal Process

The development of modern and future power systems is associated with the definition of new approaches for their simulation, control, and protection. To give an example, the increasing connection of massive renewable energy conversion systems is justifying the integration of DC infrastructures (eventually, multi-terminal HVDC) in the current AC power grids. Furthermore, the existing passive distribution networks are evolving by integration of decentralized and intermittent generation units which results in Active Distribution Networks (ADNs). As a consequence, complex power system topologies are emerging requiring adequate simulation tools capable to reproduce, possibly in real-time, their dynamic behavior. In this context, future operation/protection practices of power networks might rely on the availability of chip-scale real-time simulators (RTS) that will enable the implementation of efficient protection/fault location processes that, in principle, should be capable to comply with the restrictive constraints associated with these complex systems. Within this context, the work presented in the thesis contributes to the integration of new concepts of the fault location in AC/DC systems that can be deployed in chip-scale real-time simulation hardware represented by Field Programmable Gate Arrays (FPGAs). The development of the proposed fault location platform is done in two steps. First, an original fault location method based on the Electromagnetic Time Reversal (EMTR) theory is proposed. The proposed method is validated for the case of various power networks topologies and its performance is assessed. Compared to the existing fault location methods, the proposed approach is suitably applicable to different topologies including MTDCs and ADNs. Next, a new automated FPGA-based solver for RTS is proposed. The developed FPGA-RTS uses a specific automated procedure to couple the simulation platform with an offline simulation environment (EMTR-RV) without the need for Hardware Description Language (HDL). It is able to simulate both power electronics converters and power system grids and thanks to the use of particular parallel computational algorithms, it can accurately simulate, in real-time, Electromagnetic Transient (EMT) phenomena taking place in power converters and travelling wave propagation along multi-conductor transmission lines within very small simulation time steps (in the order of some hundreds of nanoseconds). To overcome the limitations associated with the Fixed Admittance Matrix Nodal Method (FAMNM), a method to assess the optimal value of the parameter of the Associated Discrete Circuit (ADC) switch model used by FAMNM is proposed. Finally, a specific application of the developed FPGA-RTS is explored for the development of a fault location platform by leveraging the EMTR theory. To this end, the proposed EMTR-based fault location method is integrated with the FPGA-RTS to develop an efficient fault location platform. Thanks to the fast EMT simulation capability of the FPGA-RTS, the developed fault location platform is able to estimate the accurate fault location within very short time scales. Moreover, the developed platform is compatible with the constraints characterizing complex topologies such as MTDC networks (e.g., the ultra-fast operation of the protection systems). The developed fault location platform is validated by making reference to an MTDC grid and an ADN, and it is shown to exhibit remarkable fault location accuracy as well as robustness against uncertainties such as fault type, the presence of noise, measurement systems delay, and fault impedance

Voltage Sag Ride-Through and Harmonics Mitigation for Adjustable Speed Drives using Dual-Functional Hardware

Great portion of today's industry are Adjustable Speed Drives (ASD's) operated in order to fulfill certain processes. When these processes are critical ones or sensitive to voltage disturbances, that might take place due to inserting high load in an area near to the Point of Common Coupling (PCC) of the process or due to a short term outage, few tens of thousands up to millions of dollars will be lost once such interruptions (voltage sags) take place as a result of the process failure. On the other hand, a distorted voltage waveform at the PCC for some sensitive process might malfunction as a result of the high harmonic content of the voltage waveform. Utilities are required to deliver as pure as possible sinusoidal voltage waveform according to certain limits; thus, they might apply fines against the consumers who are responsible for producing high amounts of current harmonics that affect the voltage wave shape at the PCC in order to force them to improve the consumer's load profile by adding filters at PCC for instance. Utilities are charging the consumers who are drawing power at poor power factor as well. This thesis presents an ASD retrofitted with a dual-functional piece of hardware connected in series to its DC-link that is capable of handling the previously two mentioned problems. In other words, hardware that is capable of providing voltage sag ride-through during the voltage sag conditions on one side, on the other side, during the normal operating conditions, it is capable to mitigate the harmonic contents of the drawn current by the ASD's rectifier and to improve the power factor. Survey on voltage sag ride-through for ASD's approaches are presented in the literature has been made. Approaches are classified as the topology utilized; first, topologies that utilizes energy storage elements that store energy to compensate the DC-link voltage with during the voltage sags, second, topologies retrofitting the DC-link itself with additional hardware to compensate the DC-link voltage. The first group is capable to provide voltage compensating during the full outages while the second can't. The presented voltage sag ride-through work of this thesis belongs to the second group. Boost converter has been used as the hardware to compensate the DC-link voltage because of its simplicity and cheap price. An adaptive linear network (ADALINE) is investigated as the detection system to detect the envelope of the input voltage waveform. Once the envelope of the voltage goes below a certain level, the boost converter is activated to compensate the difference between voltage set point and the actual DC-link voltage. Simulation results supporting the proposed configuration are presented. A third-harmonic current injection approach is utilized in this work in order to achieve total harmonic distortion (THD) mitigation from 32% to 5. 125% (theoretically). Two third-harmonic current injection networks have been investigated; one utilizes a real resistor, the other utilizes a resistor emulator to reduce the energy dissipated. The proposed controller for the resistor emulator does not require a proportional-integral (PI) controller. As a result of the common devices between the voltage sag ride-through circuitry and the harmonic mitigation one, they can be integrated together in one circuitry connected in series with the DC-link of the ASD. And hence, the dual functionality of the hardware will be achieved. Simulation results supporting the theoretical results have been presented