Generic Methodology for Formal Verification of UML Models

This paper discusses a Unified Modelling Language (UML) based formal verification methodology for early error detection in the model-based software development cycle. Our approach proposes a UML-based formal verification process utilising functional and behavioural modelling artifacts of UML. It reinforces these artifacts with formal model transition and property verification. The main contribution is a UML to Labelled Transition System (LTS) Translator application that automatically converts UML Statecharts to formal models. Property specifications are derived from system requirements and corresponding Computational Tree Logic (CTL)/Linear Temporal Logic (LTL) model checking procedure verifies property entailment in LTS. With its ability to verify CTL and LTL specifications, the methodology becomes generic for verifying all types of embedded system behaviours. The steep learning curve associated with formal methods is avoided through the automatic formal model generation and thus reduces the reluctance of using formal methods in software development projects. A case study of an embedded controller used in military applications validates the methodology. It establishes how the methodology finds its use in verifying the correctness and consistency of UML models before implementation

Methodology for Integrating Computational Tree Logic Model Checking in Unified Modelling Language Artefacts A Case Study of an Embedded Controller

A unified modelling language (UML) based formal verification methodology that can be easily integrated into an embedded system software development life cycle is suggested. The approach augments UML diagrams with formal models through an interfacing domain and adds semantics to these diagrams. The suggested methodology; commences from functional specification and use case modelling, selects the most critical behaviour where formal verification can add value to the development cycle, analyses the selected behaviour using UML state transition diagram, derives a state chart matrix from the same, and a high level language software translates the state chart matrix to a labelled transition system. Safety properties are derived from system specifications and are expressed as computation tree logic (CTL) formulae. CTL model-checking algorithm from the literature is used for model- checking. The applicability of the suggested approach is established using a safety critical embedded controller used for deployment and recovery of sensor structures from an airborne platform

Ontology-Based Verification of UML Class/OCL Model

Software models describe structures, relationships and features of the software. Modern software development methodologies such as MDE (Model Driven Engineering) use models as core elements. In MDE, the code is automatically generated from the model and model errors can implicitly shift into the code, which are difficult to find and fix. Model verification is a promising solution to this problem. However, coverage of all facets of model verification is a painful job and existing formal/semi-formal verification methods are greatly inspired by mathematics and difficult to understand by the software practitioners. This work considers particularly UML Class/OCL (Unified Modeling Language Class/Object Constraint Language) model and presents an ontology-based verification method. In the proposed method, a class diagram is transformed into ontology specified in OWL (Web Ontology Language) and constraints into SPARQL NAF (Negation as Failure) queries. This work tries to demonstrate that the proposed approach can efficiently cover all aspects of UML Class/OCL model verification

Proceedings of the Doctoral Consortium in Computer Science (JIPII 2021)

Actas de las Jornadas de Investigación Predoctoral en Ingeniería InformáticaThis volume contains the proceedings of the Primeras Jornadas de Investigación Predoctoral en Ingeniería Informática - First Doctoral Consortium in Computer Science, JIPII 2021, which was held online on June 15th, 2021. The aim of JIPII 2021 was to provide a forum for PhD students to present and discuss their research under the guidance of a panel of senior researchers. The advances in their PhD theses under development in the Doctoral Program in Computer Science were presented in the Consortium. This Doctoral Program belongs to the Doctoral School of the University of Cadiz (EDUCA). Different stages of research were covered, from the most incipient phase, such as the PhD Thesis plans (or even a Master’s Thesis), to the most advanced phases in which the defence of the PhD Thesis is imminent. We enjoyed twenty very nice and interesting talks, organized in four sessions. We had a total of fifty participants, including speakers and attendees, with an average of thirty-two people in the morning sessions and an average of twenty people in the afternoon sessions. Several people contributed to the success of JIPII 2021. We are grateful to the Academic Committee of the Doctoral Program in Computer Science and the School of Engineering for their support. We would like also to thank the Program Committee for their work in reviewing the papers, as well as all the students and supervisors for their interest and participation. Finally, the proceedings have been published by the Department of Computer Science and Engineering. We hope that you find the proceedings useful, interesting, and challenging

A Security Verification Framework for SysML Activity Diagrams

UML and SysML play a central role in modern software and systems engineering. They are considered as the de facto standard for modeling software and systems. Today’s systems are created from a myriad of interacting parts that are combined to produce visible behavior. The main difficulty arises from the different ways in modeling each component and the way they interact with each other. Moreover, nowadays secure software has become an essential part in industrial development. One challenge in academia as well as in industry is to produce a secure product. Another challenge is to prove its correctness especially when the software environment is imprecise and uncertain. The aim of this thesis is to provide a practical and formal framework that enables security risk assessment and security requirements verification on a system modeled as a composition of UML/SysML behavioral diagrams. Our main contribution is a novel approach to automatically verify security of systems on their design models based on security requirements, probabilistic adversarial interactions between potential attackers and the system’s models. These structures are shaped to provide an elegant way to define the combination between different kinds of diagrams. We rely on stochastic security templates to specify security properties and a standard catalogue of attack patterns to build a library of attacks design patterns. The result of the interaction between selected attack scenarios and the composed diagrams with the instantiated security properties are used to quantify security risk by applying probabilistic model-checker. To handle the verification process scalability, our approach allows the verification of large system efficiently by optimizing and avoiding the global model construction. To demonstrate the effectiveness of our approach, we apply our methodology on academia as well as industrial benchmarks

Towards the Correctness of Software Behavior in UML: A Model Checking Approach Based on Slicing

Embedded systems are systems which have ongoing interactions with their environments, accepting requests and producing responses. Such systems are increasingly used in applications where failure is unacceptable: traffic control systems, avionics, automobiles, etc. Correct and highly dependable construction of such systems is particularly important and challenging. A very promising and increasingly attractive method for achieving this goal is using the approach of formal verification. A formal verification method consists of three major components: a model for describing the behavior of the system, a specification language to embody correctness requirements, and an analysis method to verify the behavior against the correctness requirements. This Ph.D. addresses the correctness of the behavioral design of embedded systems, using model checking as the verification technology. More precisely, we present an UML-based verification method that checks whether the conditions on the evolution of the embedded system are met by the model. Unfortunately, model checking is limited to medium size systems because of its high space requirements. To overcome this problem, this Ph.D. suggests the integration of the slicing (reduction) technique