Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s Successive Approximation Register ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply unique challenges arise that are met with innovation in the sample switch and comparator design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

Ultra-Low Power ADCs for Space Sensors and Instruments

A 28nm 0.1V 10-bit 2kS/s time domain ADC design is proposed. This design opens the doors to both low supply and low power space sensors and instruments. Due to the stringent voltage supply, unique challenges arise that are met with innovation in the sample switch and the quantizer design. These components of the ADC architecture are optimized to perform successfully at a 0.1V supply with a sample rate suitable for most sensor applications

A 2 GHz Bandpass Analog to Digital Delta-sigma Modulator for CDMA Receivers with 79 DB Dynamic Range in 1.23 MHz Bandwidth

This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator that can be used in wireless CDMA receivers. The continuous-time delta-sigma modulator samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The continuous-time delta-sigma modulator was fabricated in a 0.18- m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm2 . The delta-sigma modulator\u27s critical performance specifications are derived from the CDMA receiver specifications

Integrated Circuit Design for Radiation Sensing and Hardening.

Beyond the 1950s, integrated circuits have been widely used in a number of electronic devices surrounding people’s lives. In addition to computing electronics, scientific and medical equipment have also been undergone a metamorphosis, especially in radiation related fields where compact and precision radiation detection systems for nuclear power plants, positron emission tomography (PET), and radiation hardened by design (RHBD) circuits for space applications fabricated in advanced manufacturing technologies are exposed to the non-negligible probability of soft errors by radiation impact events. The integrated circuit design for radiation measurement equipment not only leads to numerous advantages on size and power consumption, but also raises many challenges regarding the speed and noise to replace conventional design modalities. This thesis presents solutions to front-end receiver designs for radiation sensors as well as an error detection and correction method to microprocessor designs under the condition of soft error occurrence. For the first preamplifier design, a novel technique that enhances the bandwidth and suppresses the input current noise by using two inductors is discussed. With the dual-inductor TIA signal processing configuration, one can reduce the fabrication cost, the area overhead, and the power consumption in a fast readout package. The second front-end receiver is a novel detector capacitance compensation technique by using the Miller effect. The fabricated CSA exhibits minimal variation in the pulse shape as the detector capacitance is increased. Lastly, a modified D flip-flop is discussed that is called Razor-Lite using charge-sharing at internal nodes to provide a compact EDAC design for modern well-balanced processors and RHBD against soft errors by SEE.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111548/1/iykwon_1.pd

A Systematic approach to determining the duty cycle for regenerative comparator used in WSN

A low power regenerative comparator is very usefulin Successive Approximation Register (SAR) type Analog toDigital Converter (ADC) for a Wireless Sensor Node (WSN).A regenerative type comparator generates output pulses bycomparing input with a reference input. This paper deals withcontrol of a power with an adjustable duty cycle. The regenerativecomparator with an adjustable duty cycle and a positive feedbackof a latch will help in improving accuracy, speed and also inachieving the less power consumption. The optimum value ofa duty cycle is determined with taking into consideration ofmetastability timing constraints. The proposed low power regenerativecomparator circuit is designed and simulated by usingTSMC 180 nm CMOS technology. The comparator consumespower as low as 298.54 nW with a regenerative time 264 ps at 1V power supply

Configurable pseudo noise radar imaging system enabling synchronous MIMO channel extension

In this article, we propose an evolved system design approach to ultra-wideband (UWB) radar based on pseudo-random noise (PRN) sequences, the key features of which are its user-adaptability to meet the demands provided by desired microwave imaging applications and its multichannel scalability. In light of providing a fully synchronized multichannel radar imaging system for short-range imaging as mine detection, non-destructive testing (NDT) or medical imaging, the advanced system architecture is presented with a special focus put on the implemented synchronization mechanism and clocking scheme. The core of the targeted adaptivity is provided by means of hardware, such as variable clock generators and dividers as well as programmable PRN generators. In addition to adaptive hardware, the customization of signal processing is feasible within an extensive open-source framework using the Red Pitaya ® data acquisition platform. A system benchmark in terms of signal-to-noise ratio (SNR), jitter, and synchronization stability is conducted to determine the achievable performance of the prototype system put into practice. Furthermore, an outlook on the planned future development and performance improvement is provided

LiDAR: reconfigurable hardware based data acquisition

Dissertação de mestrado integrado em Engenharia Eletrónica Industrial e Computadores (área de especialização em Sistemas Embebidos e Computadores)There is an expected increase in the demand for Advanced Driver-Assistance Systems (ADAS) over the next decade, incited by regulatory and consumer interest in safety applications that protect drivers and reduce accidents [1]. Even though ADAS applications are still beginning, both the OEMs and their suppliers are realizing that they could become one of the essential characteristics differentiating the various automotive brands, consequently, one of their most important revenue sources. Furthermore, the technologies used in ADAS could be used in the future to create fully autonomous vehicles, which are now becoming a major focus of research and development. There are three main sensor solutions used in ADAS. Firstly, there are optical sensors and camera based-solutions. These are the most versatile and cost-efficient solutions. However, they are easily affected by poor weather and other environmental hazards. Furthermore, they require complex software algorithms to recognize objects [1]. The second solution incorporates short and long range Radars for determining the distance, speed, and direction of objects. These sensors work better than the others in adverse weather conditions. Nonetheless there is typically a compromise between the measurement range and angle [1]. The last type of solution involves using LiDAR systems, which use laser pulses to scan the surroundings and generate a complete and precise three-dimensional image of the environment. The LiDAR is less sensitive to light and weather conditions than optical systems and provides the location of the surrounding objects directly. Due to the ever-growing use of ADAS, there is a need to develop a more advanced LiDAR sensor. To answer that need and to overcome some of the limitations of the current LiDAR sensors, the Chassis Systems Control of the Bosch Group is developing an automotive LiDAR, and the current Master’s thesis is integrated in the project. In this Master’s thesis, an Acquisition System for Bosch’s LiDAR sensor was developed. For measuring the Time-of-Flight of the laser pulses of the LiDAR, to do so multiple TDC Peripherals were developed in an FPGA platform. The measurement precision of the developed Acquisition System varies between 232.17 ps and 188.66 ps, with an average precision of 207.47 ps.É expectável que nas próximas décadas exista um aumento na procura das ADAS, potenciado pelos interesses dos reguladores e dos consumidores em aplicações que protejam o condutor e reduzam o número de acidentes. Tanto os OEMs, como os seus fornecedores aperceberam-se que, apesar das ADAS ainda estarem numa fase inicial, podem-se tornar uma característica diferenciadora entre as diversas marcas de automóveis, e por isso, uma das suas principais fontes de rendimento. Além disso, as tecnologias usadas nas ADAS poderão vir a ser utilizadas para criar veículos autónomos, os quais se estão a revelar como um dos principais focos da pesquisa e desenvolvimento. Existem três principais soluções de sensores usadas nas ADAS. Primeiro, existem as soluções baseadas em sensores óticos, que são as soluções mais versáteis e económicas. No entanto, este tipo de soluções é facilmente afetado pelo mau tempo e outros fatores ambientais. Para além do facto de necessitarem o uso de algoritmos complexos para reconhecerem objectos. A segunda solução incorpora o uso de RADARs de longo e curto alcance, com o objetivo de determinar a distância, velocidade e direção dos objetos. Estes sensores são pouco afetados por condições meteorológicas adversas. Porém, existe um compromisso entre o alcance e o ângulo de medição do sensor. A última solução envolve o uso de sistemas de LiDAR. Estes sistemas usam pulsos de laser para examinar meio-envolvente, de modo a gerar uma imagem tridimensional completa do mesmo. O LiDAR é menos sensível à luz e às condições meteorológicas e consegue fornecer diretamente a localização dos objetos à sua volta. Devido à crescente utilização das ADAS, existe a necessidade de desenvolver sensores LiDAR mais avançados. Para suprir essa necessidade e para ultrapassar algumas das limitações dos sensores atuais, a divisão Chassis Systems Control, do grupo Bosch, está atualmente a desenvolver uma solução de um sensor LiDAR para a indústria automóvel, projeto onde se insere esta dissertação. Nesta dissertação foi desenvolvido um Sistema de Aquisição para o sensor LiDAR. Este sistema mede o TOF dos pulsos de laser usado pelo LiDAR. Para isso, vários periféricos de TDC foram desenvolvidos numa FPGA. A precisão de medição do sistema varia entre os 232.17 ps e os 188.66 ps, com um valor médio de 207.47 ps.This work is supported by European Structural and Investment Funds in the FEDER component, through the Operational Competitiveness and Internationalization Programme (COMPETE 2020) [Project nº 037902; Funding Reference: POCI-01-0247-FEDER-037902]

Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones

Mención Internacional en el título de doctorThis thesis focuses on the development of capacitive sensor readout circuits and data converters based on frequency-encoding. This research has been motivated by the needs of consumer electronics industry, which constantly demands more compact readout circuit for MEMS microphones and other sensors. Nowadays, data acquisition is mainly based on encoding signals in voltage or current domains, which is becoming more challenging in modern deep submicron CMOS technologies. Frequency-encoding is an emerging signal processing technique based on encoding signals in the frequency domain. The key advantage of this approach is that systems can be implemented using mostly-digital circuitry, which benefits from CMOS technology scaling. Frequencyencoding can be used to build phase referenced integrators, which can replace classical integrators (such as switched-capacitor based integrators) in the implementation of efficient analog-to-digital converters and sensor interfaces. The core of the phase referenced integrators studied in this thesis consists of the combination of different oscillator topologies with counters and highly-digital circuitry. This work addresses two related problems: the development of capacitive MEMS sensor readout circuits based on frequency-encoding, and the design and implementation of compact oscillator-based data converters for audio applications. In the first problem, the target is the integration of the MEMS sensor into an oscillator circuit, making the oscillation frequency dependent on the sensor capacitance. This way, the sound can be digitized by measuring the oscillation frequency, using digital circuitry. However, a MEMS microphone is a complex structure on which several parasitic effects can influence the operation of the oscillator. This work presents a feasibility analysis of the integration of a MEMS microphone into different oscillator topologies. The conclusion of this study is that the parasitics of the MEMS limit the performance of the microphone, making it inefficient. In contrast, replacing conventional ADCs with frequency-encoding based ADCs has proven a very efficient solution, which motivates the next problem. In the second problem, the focus is on the development of high-order oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical integrators and phase referenced integrators has been studied, followed by an overview of state-of-art oscillator-based converters. Then, a procedure to replace classical integrators by phase referenced integrators is presented, including a design example of a second-order oscillator based Sigma-Delta modulator. Subsequently, the main circuit impairments that limit the performance of this kind of implementations, such as phase noise, jitter or metastability, are described. This thesis also presents a methodology to evaluate the impact of phase noise and distortion in oscillator-based systems. The proposed method is based on periodic steady-state analysis, which allows the rapid estimation of the system dynamic range without resorting to transient simulations. In addition, a novel technique to analyze the impact of clock jitter in Sigma-Delta modulators is described. Two integrated circuits have been implemented in 0.13 μm CMOS technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder noise shaping using only oscillators and digital circuitry. The first testchip shows a malfunction in the digital circuitry due to the complexity of the multi-bit counters. The second chip, implemented using single-bit counters for simplicity, shows second-order noise shaping and reaches 103 dB-A of dynamic range in the audio bandwidth, occupying only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces para sensores capacitivos basados en codificación en frecuencia. Esta investigación está motivada por las necesidades de la industria, que constantemente demanda reducir el tamaño de este tipo de circuitos. Hoy en día, la adquisición de datos está basada principalmente en la codificación de señales en tensión o en corriente. Sin embargo, la implementación de este tipo de soluciones en tecnologías CMOS nanométricas presenta varias dificultades. La codificación de frecuencia es una técnica emergente en el procesado de señales basada en codificar señales en el dominio de la frecuencia. La principal ventaja de esta alternativa es que los sistemas pueden implementarse usando circuitos mayoritariamente digitales, los cuales se benefician de los avances de la tecnología CMOS. La codificación en frecuencia puede emplearse para construir integradores referidos a la fase, que pueden reemplazar a los integradores clásicos (como los basados en capacidades conmutadas) en la implementación de conversores analógico-digital e interfaces de sensores. Los integradores referidos a la fase estudiados en esta tesis consisten en la combinación de diferentes topologías de osciladores con contadores y circuitos principalmente digitales. Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos de lectura para sensores MEMS capacitivos basados en codificación temporal, y el diseño e implementación de conversores de datos compactos para aplicaciones de audio basados en osciladores. En el primer caso, el objetivo es la integración de un sensor MEMS en un oscilador, haciendo que la frecuencia de oscilación depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado midiendo la frecuencia de oscilación, lo cual puede realizarse usando circuitos en su mayor parte digitales. Sin embargo, un micrófono MEMS es una estructura compleja en la que múltiples efectos parasíticos pueden alterar el correcto funcionamiento del oscilador. Este trabajo presenta un análisis de la viabilidad de integrar un micrófono MEMS en diferentes topologías de oscilador. La conclusión de este estudio es que los parasíticos del MEMS limitan el rendimiento del micrófono, causando que esta solución no sea eficiente. En cambio, la implementación de conversores analógico-digitales basados en codificación en frecuencia ha demostrado ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente problema. La segunda cuestión está centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado la equivalencia entre los integradores clásicos y los integradores referidos a la fase, seguido de una descripción de los conversores basados en osciladores publicados en los últimos años. A continuación se presenta un procedimiento para reemplazar integradores clásicos por integradores referidos a la fase, incluyendo un ejemplo de diseño de un modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente se describen los principales problemas que limitan el rendimiento de este tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad. Esta tesis también presenta un nuevo método para evaluar el impacto del ruido de fase y de la distorsión en sistemas basados en osciladores. El método propuesto está basado en simulaciones PSS, las cuales permiten la rápida estimación del rango dinámico del sistema sin necesidad de recurrir a simulaciones temporales. Además, este trabajo describe una nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta. En esta tesis se han implementado dos circuitos integrados en tecnología CMOS de 0.13 μm, con el fin de demostrar la viabilidad de los moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han sido diseñados para producir conformación espectral de ruido de segundo orden, usando únicamente osciladores y circuitos mayoritariamente digitales. El primer chip ha mostrado un error en el funcionamiento de los circuitos digitales debido a la complejidad de las estructuras multi-bit utilizadas. El segundo chip, implementado usando contadores de un solo bit con el fin de simplificar el sistema, consigue conformación espectral de ruido de segundo orden y alcanza 103 dB-A de rango dinámico en el ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Georges G.E. Gielen.- Secretario: José Manuel de la Rosa.- Vocal: Ana Rus

Design of hardware-based security solutions for interconnected systems

Among all the different research lines related to hardware security, there is a particular topic that strikingly attracts attention. That topic is the research regarding the so-called Physical Unclonable Functions (PUF). The PUFs, as can be seen throughout the Thesis, present the novel idea of connecting digital values uniquely to a physical entity, just as human biometrics does, but with electronic devices. This beautiful idea is not free of obstacles, and is the core of this Thesis. It is studied from different angles in order to better understand, in particular, SRAM PUFs, and to be able to integrate them into complex systems that expand their potential. During Chapter 1, the PUFs, their properties and their main characteristics are defined. In addition, the different types of PUFs, and their main applications in the field of security are also summarized. Once we know what a PUF is, and the types of them we can find, throughout Chapter 2 an exhaustive analysis of the SRAM PUFs is carried out, given the wide availability of SRAMs today in most electronic circuits (which dramatically reduces the cost of deploying any solution). An algorithm is proposed to improve the characteristics of SRAM PUFs, both to generate identifiers and to generate random numbers, simultaneously. The results of this Chapter demonstrates the feasibility of implementing the algorithm, so in the following Chapters it is explored its integration in both hardware and software systems. In Chapter 3 the hardware design and integration of the algorithm introduced in Chapter 2 is described. The design is presented together with some examples of use that demonstrate the possible practical realizations in VLSI designs. In an analogous way, in Chapter 4 the software design and integration of the algorithm introduced in Chapter 2 is described. The design is presented together with some examples of use that demonstrate the possible practical realizations in low-power IoT devices. The algorithm is also described as part of a secure firmware update protocol that has been designed to be resistant to most current attacks, ensuring the integrity and trustworthiness of the updated firmware.In Chapter 5, following the integration of PUF-based solutions into protocols, PUFs are used as part of an authentication protocol that uses zero-knowledge proofs. The cryptographic protocol is a Lattice-based post-quantum protocol that guarantees the integrity and anonymity of the identity generated by the PUF. This type of architecture prevents any type of impersonation or virtual copy of the PUF, since this is unknown and never leaves the device. Specifically, this type of design has been carried out with the aim of having traceability of identities without ever knowing the identity behind, which is very interesting for blockchain technologies. Finally, in Chapter 6 a new type of PUF, named as BPUF (Behavioral and Physical Unclonable Function), is proposed and analyzed according to the definitions given in Chapter 1. This new type of PUF significantly changes the metrics and concepts to which we were used to in previous Chapters. A new multi-modal authentication protocol is presented in this Chapter, taking advantage of the challenge-response tuples of BPUFs. An example of BPUFs is illustrated with SRAMs. A proposal to integrate the BPUFs described in Chapter 6 into the protocol of Chapter 5, as well as the final remarks of the Thesis, can be found in Chapter 7