Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers

Circuit Techniques for Adaptive and Reliable High Performance Computing.

Increasing power density with process scaling has caused stagnation in the clock speed of modern microprocessors. Accordingly, designers have adopted message passing and shared memory based multicore architectures in order to keep up with the rapidly rising demand for computing throughput. At the same time, applications are not entirely parallel and improving single-thread performance continues to remain critical. Additionally, reliability is also worsening with process scaling, and margining for failures due to process and environmental variations in modern technologies consumes an increasingly large portion of the power/performance envelope. In the wake of multicore computing, reliability of signal synchronization between the cores is also becoming increasingly critical. This forces designers to search for alternate efficient methods to improve compute performance while addressing reliability. Accordingly, this dissertation presents innovative circuit and architectural techniques for variation-tolerance, performance and reliability targeted at datapath logic, signal synchronization and memories. Firstly, a domino logic based design style for datapath logic is presented that uses Adaptive Robustness Tuning (ART) in addition to timing speculation to provide up to 71% performance gains over conventional domino logic in 32bx32b multiplier in 65nm CMOS. Margins are reduced until functionality errors are detected, that are used to guide the tuning. Secondly, for signal synchronization across clock domains, a new class of dynamic logic based synchronizers with single-cycle synchronization latency is presented, where pulses, rather than stable intermediate voltages cause metastability. Such pulses are amplified using skewed inverters to improve mean time between failures by ~1e6x over jamb latches and double flip-flops at 2GHz in 65nm CMOS. Thirdly, a reconfigurable sensing scheme for 6T SRAMs is presented that employs auto-zero calibration and pre-amplification to improve sensing reliability (by up to 1.2 standard deviations of NMOS threshold voltage in 28nm CMOS); this increased reliability is in turn traded for ~42% sensing speedup. Finally, a main memory architecture design methodology to address reliability and power in the context of Exascale computing systems is presented. Based on 3D-stacked DRAMs, the methodology co-optimizes DRAM access energy, refresh power and the increased cost of error resilience, to meet stringent power and reliability constraints.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/107238/1/bharan_1.pd

Integration of dual-clutch transmissions in hybrid electric vehicle powertrains

This dissertation presents a study focused on exploring the integration of Dual-Clutch Transmissions (DCTs) in Hybrid Electric Vehicles (HEVs). Among the many aspects that could be investigated regarding the electrification of DCTs, research efforts are undertaken here to the development of control strategies for improving vehicle dynamic performance during gearshifts and the energy management of HEVs. In the first part of the dissertation, control algorithms for upshift and downshift maneuvers are developed for a Plug-in Hybrid Electric Vehicle (PHEV) architecture in which an electric machine is connected to the output of the transmission, thus obtaining torque filling capabilities during gearshifts. Promising results, in terms of the vehicle dynamic performance, are obtained for the two transmission systems analyzed: Hybrid Automated Manual Transmission (H-AMT) and Hybrid Dual-Clutch Transmission (H-DCT). On the other hand, the global optimal solution to the energy management problem for a PHEV equipped with a DCT is found by developing a detailed Dynamic Programing (DP) formulation. The main control objective is to reduce the fuel consumption during a driving mission. Based on the DP results, a novel real-time implementable Energy Management Strategy (EMS) is proposed. The performance of such controller, in terms of the overall fuel usage, is close to that of the optimal solution. Furthermore, the developed approach is shown to outperform a well-known causal strategy: Adaptive Equivalent Consumption Minimization Strategy (A-ECMS). One of the main aspects that differentiates the EMSs proposed here to those presented in previous works is the introduction of a model to estimate the energy consumption during gearshifts in DCTs. Thus, this dissertation illustrates how through the electrification of powertrains equipped with DCTs both the vehicle dynamic performance and the energy consumption can be improved

An Energy-Efficient System with Timing-Reliable Error-Detection Sequentials

A new type of energy-efficient digital system that integrate EDS and DVS circuits has been developed. In these systems, EDS-monitored paths convert the PVT variations into timing variations. Nevertheless, the conversion can suffer from the reliability issue (extrinsic EDS-reliability). EDS circuits detect the unfavorable timing variations (so called ``error'') and guide DVS circuits to adjust the operating voltage to a proper lower level to save the energy. However, the error detection is generally susceptible to the metastability problem (intrinsic EDS-reliability) due to the synchronizer in EDS circuits. The MTBF due to metastability is exponentially related to the synchronizer delay. This dissertation proposes a new EDS circuit deployment strategy to enhance the extrinsic EDS-reliability. This strategy requires neither buffer insertion nor an extra clock and is applicable for FPGA implementations. An FPGA-based Discrete Cosine Transform with EDS and DVS circuits deployed in this fashion demonstrates up to 16.5\% energy savings over a conventional design at equivalent frequency setting and image quality, with a 0.8\% logic element and 3.5\% maximum frequency penalties. VBSs are proposed to improve the synchronizer delay under single low-voltage supply environments. A VBS consists of a Jamb latch and a switched-capacitor-based charge pump that provides a voltage boost to the Jamb Latch to speed up the metastability resolution. The charge pump can be either CVBS or MVBS. A new methodology for extracting the metastability parameters of synchronizers under changing biasing currents is proposed. For a 1-year MTBF specification, MVBS and CVBS show 2.0 to 2.7 and 5.1 to 9.8 times the delay improvement over the basic Jamb latch, respectively, without large power consumption. Optimization techniques including transistor sizing, FBB and dynamic implementation are further applied. For a common MTBF specification at typical PVT conditions, the optimized MVBS and CVBS show 2.97 to 7.57 and 4.14 to 8.13 times the delay improvement over the basic Jamb latch, respectively. In post-Layout simulations, MVBS and CVBS are 1.84 and 2.63 times faster than the basic Jamb latch, respectively

Design of variation-tolerant synchronizers for multiple clock and voltage domains

PhD ThesisParametric variability increasingly affects the performance of electronic circuits as the fabrication technology has reached the level of 32nm and beyond. These parameters may include transistor Process parameters (such as threshold voltage), supply Voltage and Temperature (PVT), all of which could have a significant impact on the speed and power consumption of the circuit, particularly if the variations exceed the design margins. As systems are designed with more asynchronous protocols, there is a need for highly robust synchronizers and arbiters. These components are often used as interfaces between communication links of different timing domains as well as sampling devices for asynchronous inputs coming from external components. These applications have created a need for new robust designs of synchronizers and arbiters that can tolerate process, voltage and temperature variations. The aim of this study was to investigate how synchronizers and arbiters should be designed to tolerate parametric variations. All investigations focused mainly on circuit-level and transistor level designs and were modeled and simulated in the UMC90nm CMOS technology process. Analog simulations were used to measure timing parameters and power consumption along with a “Monte Carlo” statistical analysis to account for process variations. Two main components of synchronizers and arbiters were primarily investigated: flip-flop and mutual-exclusion element (MUTEX). Both components can violate the input timing conditions, setup and hold window times, which could cause metastability inside their bistable elements and possibly end in failures. The mean-time between failures is an important reliability feature of any synchronizer delay through the synchronizer. The MUTEX study focused on the classical circuit, in addition to a number of tolerance, based on increasing internal gain by adding current sources, reducing the capacitive loading, boosting the transconductance of the latch, compensating the existing Miller capacitance, and adding asymmetry to maneuver the metastable point. The results showed that some circuits had little or almost no improvements, while five techniques showed significant improvements by reducing τ and maintaining high tolerance. Three design approaches are proposed to provide variation-tolerant synchronizers. wagging synchronizer proposed to First, the is significantly increase reliability over that of the conventional two flip-flop synchronizer. The robustness of the wagging technique can be enhanced by using robust τ latches or adding one more cycle of synchronization. The second approach is the Metastability Auto-Detection and Correction (MADAC) latch which relies on swiftly detecting a metastable event and correcting it by enforcing the previously stored logic value. This technique significantly reduces the resolution time down from uncertain synchronization technique is proposed to transfer signals between Multiple- Voltage Multiple-Clock Domains (MVD/MCD) that do not require conventional level-shifters between the domains or multiple power supplies within each domain. This interface circuit uses a synchronous set and feedback reset protocol which provides level-shifting and synchronization of all signals between the domains, from a wide range of voltage-supplies and clock frequencies. Overall, synchronizer circuits can tolerate variations to a greater extent by employing the wagging technique or using a MADAC latch, while MUTEX tolerance can suffice with small circuit modifications. Communication between MVD/MCD can be achieved by an asynchronous handshake without a need for adding level-shifters.The Saudi Arabian Embassy in London, Umm Al-Qura University, Saudi Arabi

A Novel Approach of Synchronization of Microgrid with a Power System of Limited Capacity

Currently, active networks called microgrids are formed on the basis of local power supply systems with a small share of distributed generation. Microgrids operating in an island mode, in some cases, have the ability to transfer electricity excess to an external network leading to a synchronization requirement; thus, the optimization task in terms of the system’s synchronization must be considered. This paper proposes a method for obtaining synchronization between microgrids and power systems of limited capacity based on a passive synchronization algorithm, allowing us to connect a microgrid to an external power system with a minimum impact moment on the shaft of the generating equipment. The algorithm application was demonstrated by considering a real-life object in Tajikistan. The simulation was carried out on RastrWin3. The obtained results show that the microgrid generator is connected to an external power system at an angle of 0.3◦ and a power surge of 29 kW, unlike the classical synchronization algorithm with an angle of 6.8◦ and a power surge of 154 kW (a reduction of the shock moment by more than five times). The proposed synchronization method allows us to reduce the resource consumption of the generating equipment and increase the reliability and efficiency of the functioning units of the examined power system. © 2021 by the authors. Licensee MDPI, Basel, Switzerland

"Design and verification of a digitally controlled output stage for automotive safety applications"

In these last decades the importance of electronics in automotive environment had an exponential increase. Electronic Integrated Circuits (ICs) are now playing a primary role in the economy of vehicles, especially since special laws and strict safety requirements have been introduced. The aim of the thesis, developed within Austramicrosystem design centre of Navacchio (PI), is the design and the verification of a digitally controlled output stage. Output stages are the final components of many sensor-based ICS. In fact their typical typical signal-chain starts from the sensing of a physical phenomenon, passing by its transduction in an electrical quantity, its digital conversion and processing, and ends with the drive of an actuator. The task of an output stage is to interpret the input digital signal and consequently drive an actuator. The target of this work was to improve the performances of the current output stage company solutions. This target has been achieved through the development and realization of a digitally-controlled loop. The proposed solution guarantees a performance improvement and adds the possibility to cyclically monitor the output voltage, detecting issues and reporting errors. A control algorithm has been developed and validated through its insertion in a mathematical modeling of the system. Then, to experimentally validate this control algorithm, an Integrated Circuit has been designed, realized and lastly measured. This thesis follows the workflow behind the realization of the Integrated Circuit and its successive measurement

Simulation and Optimization of Wet Double Clutch Transmission (DCT)

This work focused on the longitudinal 7-speed wet DCT that is used by some high performance sport cars due to its capability to handle high rpm and torque output engine. This capability is coming from the use of wet friction clutch which able to dissipate more heat generated by high torque engine in slipping clutch during engagement process. One of inefficiency comes from the use of clutch fluid which tends to stick the clutch pairs, causing the drag torque when the fluid sheared by the clutch pair that rotates with different speed after the gear preselects action. The other drawback is occurred in the manual shift mode when the next gear that automatically preselected by the TCU before the gear shift is unmatched to the next gear as wished by the driver. The research was done to overcome the explained wet DCT drawback by improving the gear preselect action strategy so-called the seamless gear preselect strategy. This new strategy is achieved by improving the software of control algorithm rather than the DCT hardware for cost efficiency through software in the loop (SiL) method. This new strategy was achieved by simultaneously activate the gear preselect action during the fast filling phase of the ongoing clutch hydraulic system. The new gear preselect strategy make the reduction of unnecessary drag torque that normally occurs in wet DCT after gear preselect action in steady condition. The state of the art focusing on the subject of DCT construction, empiric system modeling, objectification and optimization method that were presented using a simulation environment to prepare the virtual gear shift optimization. After the model is fully confirmed, the optimization of wet DCT gear shift using genetic algorithm method was explained to meet the optimization objectives including the shift qualities, the uninterrupted torque during gear shifting and the limited heat generated as losses energy. The new gear preselect strategy is superior particularly for manual gear shift mode. The proposed strategy was carefully prepared in regards to the capability of the particular wet DCT construction particularly the hydraulic valve and gear shift actuator structure, while this optimization was done on the software basis alone without any further modification on the hardware. The optimization result confirmed the new gear preselect strategy is possible to be adapted in the particular seven speed wet DCT.Die Arbeit hatte ihren Schwerpunkt auf dem 7-Gang-nassen-DKG, welches von einigen Hochleistungssportwagen genutzt wird aufgrund dessen Fähigkeit, hochdrehenden und drehmomentstarken Motoren standhalten zu können. Diese Fähigkeit liegt begründet in der Verwendung einer nass Doppelkupplung, die mehr Hitze abführen kann, welche in einem drehmomentstarken Motor durch Rutschkupplung beim Einkuppeln entsteht. Eine der Ineffizienzen beruht auf der Nutzung von Kupplungsflüssigkeit. Diese neigt dazu, die Kupplungspaare zusammenzukleben, welches ein Schleppmoment verursacht, weil das gescherte Öl des Kupplungspaares nach der Gangvorwahl mit einer veränderten Geschwindigkeit rotiert. Der weitere Nachteil liegt im manuellen Schalten, wenn der Gang, welcher automatisch von der TCU vorgewählt wurde, nicht dem vom Fahrer gewünschten Gang entspricht. Die Forschung wurde durchgeführt, um den geschilderten Nachteil der Nass-DKG zu eliminieren durch den Gangvorwahl Strategie verbessert die nahtlose-Gangvorwahl Strategie sogenannte. Diese neue Strategie wird dadurch erreicht, indem lediglich der Kontrollalgorithmus verbessert werden musste, und nicht etwa die DKG-Hardware, zum kosteneffizienten Zweck durch die Software in the Loop Methode. Diese neue Strategie wurde durch gleichzeitig erreicht das Gangvorwahl während der schnellen Füllphase der laufenden Kupplung Hydrauliksystem aktivieren. Darüber hinaus macht die neue Gangvorwahl Strategie, um die Reduzierung unnötiger Schleppmoment, das in nassen DKG erfolgt in der Regel nach der Gangvorwahl Aktion im stationären Zustand. Der Stand der Technik in Bezug auf Fokussierung auf die Themen DKG-Konstruktion, empirisches Modellierungssystem, Versachlichung und Optimierung wurde während einer Simulation vorgestellt, um die virtuelle Gang-Auswahl vorzubereiten. Weiterhin wurde die Fahrzeugbeschleunigung während der Gangwechsel als Simulationsergebnis bewertet, um die Spontanitäts- und Schaltkomfortwerte durch eine Objektivierungsmethode zu erhalten. Das neue Gangvorwahl-Strategie überlegen ist besonders für den manuellen Gangschaltmodus. Die vorgeschlagene Strategie wurde im Hinblick auf die Fähigkeit der DKG-Konstruktion, insbesondere des Hydraulikventils und der Gangschaltungsaktuator-Struktur, gewählt, während die Optimierung allein auf Softwarebasis ohne jegliche weitere Änderung an der Hardware durchgeführt wurde. Das Optimierungsergebnis hat bestätigt, dass die neue Gangvorwahl-Strategie geeignet ist zur Anwendung in der DKG

Simulation and Optimization of Wet Double Clutch Transmission (DCT)

This work focused on the longitudinal 7-speed wet DCT that is used by some high performance sport cars due to its capability to handle high rpm and torque output engine. This capability is coming from the use of wet friction clutch which able to dissipate more heat generated by high torque engine in slipping clutch during engagement process. One of inefficiency comes from the use of clutch fluid which tends to stick the clutch pairs, causing the drag torque when the fluid sheared by the clutch pair that rotates with different speed after the gear preselects action. The other drawback is occurred in the manual shift mode when the next gear that automatically preselected by the TCU before the gear shift is unmatched to the next gear as wished by the driver. The research was done to overcome the explained wet DCT drawback by improving the gear preselect action strategy so-called the seamless gear preselect strategy. This new strategy is achieved by improving the software of control algorithm rather than the DCT hardware for cost efficiency through software in the loop (SiL) method. This new strategy was achieved by simultaneously activate the gear preselect action during the fast filling phase of the ongoing clutch hydraulic system. The new gear preselect strategy make the reduction of unnecessary drag torque that normally occurs in wet DCT after gear preselect action in steady condition. The state of the art focusing on the subject of DCT construction, empiric system modeling, objectification and optimization method that were presented using a simulation environment to prepare the virtual gear shift optimization. After the model is fully confirmed, the optimization of wet DCT gear shift using genetic algorithm method was explained to meet the optimization objectives including the shift qualities, the uninterrupted torque during gear shifting and the limited heat generated as losses energy. The new gear preselect strategy is superior particularly for manual gear shift mode. The proposed strategy was carefully prepared in regards to the capability of the particular wet DCT construction particularly the hydraulic valve and gear shift actuator structure, while this optimization was done on the software basis alone without any further modification on the hardware. The optimization result confirmed the new gear preselect strategy is possible to be adapted in the particular seven speed wet DCT.Die Arbeit hatte ihren Schwerpunkt auf dem 7-Gang-nassen-DKG, welches von einigen Hochleistungssportwagen genutzt wird aufgrund dessen Fähigkeit, hochdrehenden und drehmomentstarken Motoren standhalten zu können. Diese Fähigkeit liegt begründet in der Verwendung einer nass Doppelkupplung, die mehr Hitze abführen kann, welche in einem drehmomentstarken Motor durch Rutschkupplung beim Einkuppeln entsteht. Eine der Ineffizienzen beruht auf der Nutzung von Kupplungsflüssigkeit. Diese neigt dazu, die Kupplungspaare zusammenzukleben, welches ein Schleppmoment verursacht, weil das gescherte Öl des Kupplungspaares nach der Gangvorwahl mit einer veränderten Geschwindigkeit rotiert. Der weitere Nachteil liegt im manuellen Schalten, wenn der Gang, welcher automatisch von der TCU vorgewählt wurde, nicht dem vom Fahrer gewünschten Gang entspricht. Die Forschung wurde durchgeführt, um den geschilderten Nachteil der Nass-DKG zu eliminieren durch den Gangvorwahl Strategie verbessert die nahtlose-Gangvorwahl Strategie sogenannte. Diese neue Strategie wird dadurch erreicht, indem lediglich der Kontrollalgorithmus verbessert werden musste, und nicht etwa die DKG-Hardware, zum kosteneffizienten Zweck durch die Software in the Loop Methode. Diese neue Strategie wurde durch gleichzeitig erreicht das Gangvorwahl während der schnellen Füllphase der laufenden Kupplung Hydrauliksystem aktivieren. Darüber hinaus macht die neue Gangvorwahl Strategie, um die Reduzierung unnötiger Schleppmoment, das in nassen DKG erfolgt in der Regel nach der Gangvorwahl Aktion im stationären Zustand. Der Stand der Technik in Bezug auf Fokussierung auf die Themen DKG-Konstruktion, empirisches Modellierungssystem, Versachlichung und Optimierung wurde während einer Simulation vorgestellt, um die virtuelle Gang-Auswahl vorzubereiten. Weiterhin wurde die Fahrzeugbeschleunigung während der Gangwechsel als Simulationsergebnis bewertet, um die Spontanitäts- und Schaltkomfortwerte durch eine Objektivierungsmethode zu erhalten. Das neue Gangvorwahl-Strategie überlegen ist besonders für den manuellen Gangschaltmodus. Die vorgeschlagene Strategie wurde im Hinblick auf die Fähigkeit der DKG-Konstruktion, insbesondere des Hydraulikventils und der Gangschaltungsaktuator-Struktur, gewählt, während die Optimierung allein auf Softwarebasis ohne jegliche weitere Änderung an der Hardware durchgeführt wurde. Das Optimierungsergebnis hat bestätigt, dass die neue Gangvorwahl-Strategie geeignet ist zur Anwendung in der DKG