Etude d'architectures et d'empilements innovants de mémoires Split-Gate (grille séparée) à couche de piégeage discret

Du fait de l'augmentation de la demande de produits pour les applications grand public, industrielles et automobiles, des mémoires embarquées fiables et à faible coût de fabrication sont de plus en plus demandées. Dans ce contexte, les mémoires split-gate à piégeage discret sont proposées pour des microcontrôleurs. Elles combinent l'avantage d'une couche de stockage discrète et de la con guration split-gate. Durant ce travail de recherche, des mémoires split-gate à couche de piégeage discret ayant des longueurs de grille de 20nm sont présentées pour la première fois. Celles-ci on été réalisées avec des nanocristaux de silicium (Si-nc), du nitrure de silicium (SiN) ou un hybride Si-nc/SiN avec diélectrique de control de type SiO2 ou AlO et sont comparées en termes de performances lors des procédures d'eff acement et de rétention. Ensuite, la miniaturisation des mémoires split-gate à piégeage de charge est étudié, en particulier au travers de l'impact de la réduction de la longueur de grille sur la fenêtre de mémorisation, la rétention et la consommation. Le rôle des défauts dans le diélectrique de contrôle (alumine) utilisé dans les mémoires de type TANOS a été étudié. Des travaux ont été menés pour déterminer l'origine des pièges dans ce matériau, par le biais de la simulation atomistique ainsi que d'analyses physico-chimiques précises. Nous avons montré que la concentration de pièges dans AlO pouvait être réduite par ajustement des conditions de procédé de fabrication, débouchant ainsi sur l'amélioration de la rétention dans les mémoires à piégeage de charge. Ce résultat est convenable pour les applications de type embarquéDue to the increasing demand for consumer, industrial and automotive products, highly reliable, and low integration cost embedded memories are more and more required. In this context, split-gate charge trap memories were proposed for microcontroller products, combining the advantage of a discrete storage layer and of the split-gate con guration. In this thesis, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1st time. Silicon nanocristals (Si-nc), or silicon nitride (SiN) and hybrid Si-nc/SiN based split-gate memories, with SiO2 or AlO control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. We thus studied the role of defects on alumina control dielectric employed in TANOS-like memory. We used atomistic simulation, consolidated by a detailed alumina physico-chemical material analysis, to investigate the origin of traps in alumina. We showed that the trap concentration in AlO can be decreased by adjusting the process conditions leading to improved retention behaviour in charge trap memory, suitable for embedded applications.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Caractérisation, mécanismes et applications mémoire des transistors avancés sur SOI

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l existence et l interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif.The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO2 was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA). MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO2/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (Rs) associated with the substrate and metal contact. The interface state density (Dit), calculated by conductance method, suggests that Dit is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest Dit whereas crystallized HfO2 has the highest Dit. Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples. The reliability of TiN/ZrO2/Al2O3/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO2 by SPAO when SPAO is processed after high-k. GeO2 at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress. To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur

Afin de pouvoir continuer la miniaturisation de la brique de base des circuits électroniques, le transistor MOS, l introduction d oxyde de grille à haute permittivité était inévitable. Un empilement de type high-k/grille métal en remplacement du couple SiO2 /Poly-Si est introduit afin de limiter le courant de fuite tout en conservant un bon contrôle électrostatique du canal de conduction. L introduction de ces matériaux pose naturellement des questions de fiabilité des dispositifs obtenus et ce travail s inscrit dans ce contexte. Afin de réaliser des mesures de durée de vie sans avoir à finir les dispositifs, une méthode utilisant le C-AFM sous ultravide est proposée. Le protocole expérimental repose sur une comparaison systématique des distributions des temps de claquage obtenues à l échelle du composant et à l échelle nanométrique. La comparaison systématique des mesures s avère fiable si l on considère une surface de contact entre la pointe et le diélectrique de l ordre du nm . Des distributions de Weibull présentant une même pente et un même facteur d accélération en tension sont rapportées montrant une origine commune pour le mécanisme de rupture aux deux échelles.Une résistance différentielle négative, précédant la rupture diélectrique, est rapportée lors de mesures courant tension pour certaines conditions de rampe. Ce phénomène de dégradation de l oxyde, visible grâce au C-AFM , est expliqué et modélisé dans ce manuscrit par la croissance d un filament conducteur dans l oxyde. Ce même modèle permet aussi de décrire la rupture diélectrique.Finalement, l empilement de grille bicouche du noeud 28nm est étudié. Une preuve expérimentale montrant que la distribution du temps de claquage du bicouche est bien une fonction des caractéristiques de tenue en tension propres de chaque couche est présentée.In order to continue the scaling of the MOS transistor the replacement of the gate oxide layer by a high K/Metal gate was mandatory. From a reliability point of view, the introduction of these new materials could cause a lifetime reduction. To test the lifetime of the device a new technique using the C-AFM under Ultra High Vacuum is proposed. The experimental approach is based on a systematic comparison between the time to failure distribution obtained at device scale and at nanoscale. The comparison is reliable if we assume a contact surface of several nm under the tip. Weibull distributions with a same slope and a same voltage acceleration factor have been found exhibiting a common origin of breakdown at both scales.We have reported a negative differential resistance phenomenon during Current-Voltage measurements. This degradation phenomenon has been modelled and explained by the growth of a conductive filament in the oxide layer. This model is also able to describe the breakdown of the oxide layer.Finally the bi layer gate stack of the 28nm node was studied. The first experimental proof confirming that the lifetime distribution of the bi-layer gate stack is a function of the lifetime of each layer taken separately is presented.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

ULTRARAM™:Design, Modelling, Fabrication and Testing of Ultra-low-power III-V Memory Devices and Arrays

In this thesis, a novel memory based on III-V compound semiconductors is studied, both theoretically and experimentally, with the aim of developing a technology with superior performance capabilities to established and emerging rival memories. This technology is known as ULTRARAM™. The memory concept is based on quantum resonant tunnelling through InAs/AlSb heterostructures, which are engineered to only allow electron tunnelling at precise energy alignment(s) when a bias is applied. The memory device features a floating gate (FG) as the storage medium, where electrons that tunnel through the InAs/AlSb heterostructure are confined in the FG to define the memory logic (0 or 1). The large conduction band offset of the InAs/AlSb heterojunction (2.1 eV) keeps electrons in the FG indefinitely, constituting a non-volatile logic state. Electrons can be removed from the FG via a similar resonant tunnelling process by reversing the voltage polarity. This concept shares similarities with flash memory, however the resonant tunnelling mechanism provides ultra-low-power, low-voltage, high-endurance and high-speed switching capability. The quantum tunnelling junction is studied in detail using the non-equilibrium Green’s function (NEGF) method. Then, Poisson-Schrödinger simulations are used to design a high-contrast readout procedure for the memory using the unusual type-III band-offset of the InAs/GaSb heterojunction. With the theoretical groundwork for the technology laid out, the memory performance is modelled and a high-density ULTRARAM™ memory architecture is proposed for random-access memory applications. Later, NEGF calculations are used for a detailed study of the process tolerances in the tunnelling region required for ULTRARAM™ large-scale wafer manufacture. Using interfacial misfit array growth techniques, III-V layers (InAs, AlSb and GaSb) for ULTRARAM™ were successfully implemented on both GaAs and Si substrates. Single devices and 2×2 arrays were then fabricated using a top-down processing approach. The memories demonstrated outstanding memory performance on both substrate materials at 10, 20 and 50 µm gate lengths at room temperature. Non-volatile switching was obtained with ≤ 2.5 V pulses, corresponding to a switching energy per unit area that is lower than DRAM and flash by factors of 100 and 1000 respectively. Memory logic was retained for over 24 hours whilst undergoing over 10^6 readout operations. Analysis of the retention data suggests a storage time exceeding 1000 years. Devices showed promising durability results, enduring over 10^7 cycles without degradation, at least two orders of magnitude improvement over flash memory. Switching of the cell’s logic was possible at 500 µs pulse durations for a 20 µm gate length, suggesting a subns switching time if scaled to modern-day feature sizes. The proposed half-voltage architecture is shown to operate in principle, where the memory state is preserved during a disturbance test of > 10^5 half-cycles. With regard to the device physics, these findings point towards ULTRARAM™ as a universal memory candidate. The path towards future commercial viability relies on process development for aggressive device and array-size scaling and implementation on larger Si wafe

Gate leakage variability in nano-CMOS transistors

Gate leakage variability in nano-scale CMOS devices is investigated through advanced modelling and simulations of planar, bulk-type MOSFETs. The motivation for the work stems from the two of the most challenging issues in front of the semiconductor industry - excessive leakage power, and device variability - both being brought about with the aggressive downscaling of device dimensions to the nanometer scale. The aim is to deliver a comprehensive tool for the assessment of gate leakage variability in realistic nano-scale CMOS transistors. We adopt a 3D drift-diffusion device simulation approach with density-gradient quantum corrections, as the most established framework for the study of device variability. The simulator is first extended to model the direct tunnelling of electrons through the gate dielectric, by means of an improved WKB approximation. A study of a 25 nm square gate n-type MOSFET demonstrates that combined effect of discrete random dopants and oxide thickness variation lead to starndard deviation of up to 50% (10%) of the mean gate leakage current in OFF(ON)-state of the transistor. There is also a 5 to 6 times increase of the magnitude of the gate current, compared to that simulated of a uniform device. A significant part of the research is dedicated to the analysis of the non-abrupt bandgap and permittivity transition at the Si/SiO2 interface. One dimensional simulation of a MOS inversion layer with a 1nm SiO2 insulator and realistic band-gap transition reveals a strong impact on subband quantisation (over 50mV reduction in the delta-valley splitting and over 20% redistribution of carriers from the delta-2 to the delta-4 valleys), and enhancement of capacitance (over 10%) and leakage (about 10 times), relative to simulations with an abrupt band-edge transition at the interface

Ultrahigh vacuum plasma oxidation in the fabrication of ultrathin silicon dioxide films

This thesis discusses the fabrication and characterization of ultrathin insulator films. These are essential for nanoscale semiconductor device fabrication. When the insulator layer thickness is only a few times the molecule diameter, it is crucial that both film homogeneity and the insulator/semiconductor interface quality are as high as possible. The small dimensions must also be taken into account in characterization, because the established measurement techniques and analyses used in more traditional MOS characterization are not necessarily valid any more. In this work, the metal/silicon dioxide/silicon structure (especially oxide and oxide/semiconductor interface quality) and various silicon dioxide fabrication methods are discussed. The focus in the experimental work is on the studying the plasma assisted oxidation of silicon in an ultra high vacuum chamber and on characterizing the fabricated films. Some of the film properties are found to be excellent: interface smoothness is of a very high quality and interface state densities are low (1011 eV-1cm-2 or lower in the mid-gap) even without any annealing. Process control also seems to be good, as is the breakdown field. The oxide charge, however, is quite high. This may cause considerable harm. One of the consequences is an increased leakage current. This also significantly decreases the device life time by increasing current generated defects. In the annealing experiments carried out, the oxide charge was seen to decrease, indicating that the quality of the silicon dioxide films can be significantly improved by optimization of the thermal treatments. The molecular beam epitaxy system used in processing is designed mainly for research purposes, offering possibility to gain much information about the oxidation process itself. Other, and cheaper, thermal oxidation procedures have in recent years already been developed to a very high level, which means that the process developed is not necessarily the best choice for conventional IC manufacturing purposes. It offers, however, useful applications for research into silicon-based nanostructures, such as silicon/silicon dioxide heterostructures.reviewe

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications