A Systematic Electromagnetic-Circuit Method for EMI Analysis of Coupled Interconnects on Dispersive Dielectrics

published_or_final_versio

Compressed Passive Macromodeling

This paper presents an approach for the extraction of passive macromodels of large-scale interconnects from their frequency-domain scattering responses. Here, large scale is intended both in terms of number of electrical ports and required dynamic model order. For such structures, standard approaches based on rational approximation via vector fitting and passivity enforcement via model perturbation may fail because of excessive computational requirements, both in terms of memory size and runtime. Our approach addresses this complexity by first reducing the redundancy in the raw scattering responses through a projection and approximation process based on a truncated singular value decomposition. Then we formulate a compressed rational fitting and passivity enforcement framework which is able to obtain speedup factors up to 2 and 3 orders of magnitude with respect to standard approaches, with full control over the approximation errors. Numerical results on a large set of benchmark cases demonstrate the effectiveness of the proposed techniqu

Transient Analysis of Lossy Transmission Lines: an Efficient Approach Based on the Method of Characteristics

This paper is devoted to transient analysis of lossy transmission lines characterized by frequency-dependent parameters. A public dataset of parameters for three line examples (a module, a board, and a cable) is used, and a new example of on-chip interconnect is introduced. This dataset provides a well established and realistic benchmark for accuracy and timing analysis of interconnect analysis tools. Particular attention is devoted to the intrinsic consistency and causality of these parameters. Several implementations based on generalizations of the well-known method-of-characteristics are presented. The key feature of such techniques is the extraction of the line modal delays. Therefore, the method is highly optimized for long interconnects characterized by significant propagation delay. Nonetheless, the method is also successfully applied here to a short high/loss on-chip line, for which other approaches based on lumped matrix rational approximations can also be used with high efficiency. This paper shows that the efficiency of delay extraction techniques is strongly dependent on the particular circuit implementation and several practical issues including generation of rational approximations and time step control are discussed in detail

Worst-Case Analysis of Electrical and Electronic Equipment via Affine Arithmetic

In the design and fabrication process of electronic equipment, there are many unkown parameters which significantly affect the product performance. Some uncertainties are due to manufacturing process fluctuations, while others due to the environment such as operating temperature, voltage, and various ambient aging stressors. It is desirable to consider these uncertainties to ensure product performance, improve yield, and reduce design cost. Since direct electromagnetic compatibility measurements impact on both cost and time-to-market, there has been a growing demand for the availability of tools enabling the simulation of electrical and electronic equipment with the inclusion of the effects of system uncertainties. In this framework, the assessment of device response is no longer regarded as deterministic but as a random process. It is traditionally analyzed using the Monte Carlo or other sampling-based methods. The drawback of the above methods is large number of required samples to converge, which are time-consuming for practical applications. As an alternative, the inherent worst-case approaches such as interval analysis directly provide an estimation of the true bounds of the responses. However, such approaches might provide unnecessarily strict margins, which are very unlikely to occur. A recent technique, affine arithmetic, advances the interval based methods by means of handling correlated intervals. However, it still leads to over-conservatism due to the inability of considering probability information. The objective of this thesis is to improve the accuracy of the affine arithmetic and broaden its application in frequency-domain analysis. We first extend the existing literature results to the efficient time-domain analysis of lumped circuits considering the uncertainties. Then we provide an extension of the basic affine arithmetic to the frequency-domain simulation of circuits. Classical tools for circuit analysis are used within a modified affine framework accounting for complex algebra and uncertainty interval partitioning for the accurate and efficient computation of the worst case bounds of the responses of both lumped and distributed circuits. The performance of the proposed approach is investigated through extensive simulations in several case studies. The simulation results are compared with the Monte Carlo method in terms of both simulation time and accuracy

Addressing Computational Complexity of High Speed Distributed Circuits Using Model Order Reduction

Advanced in the fabrication technology of integrated circuits (ICs) over the last couple of years has resulted in an unparalleled expansion of the functionality of microelectronic systems. Today’s ICs feature complex deep-submicron mixed-signal designs and have found numerous applications in industry due to their lower manufacturing costs and higher performance levels. The tendency towards smaller feature sizes and increasing clock rates is placing higher demands on signal integrity design by highlighting previously negligible interconnect effects such as distortion, reflection, ringing, delay, and crosstalk. These effects if not predicted in the early stages of the design cycle can severely degrade circuit performance and reliability. The objective of this thesis is to develop new model order reduction (MOR) techniques to minimize the computational complexity of non-linear circuits and electronic systems that have delay elements. MOR techniques provide a mechanism to generate reduced order models from the detailed description of the original modified nodal analysis (MNA) formulation. The following contributions are made in this thesis: 1. The first project presents a methodology for reduction of Partial Element Equivalent Circuit (PEEC) models. PEEC method is widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. The PEEC model with retardation has been applied to 3-D analysis but often result in large and dense matrices, which are computationally expensive to solve. In this thesis, a new moment matching technique based on Multi-order Arnoldi is described to model PEEC networks with retardation. 2. The second project deals with developing an efficient model order reduction algorithm for simulating large interconnect networks with nonlinear elements. The proposed methodology is based on a multidimensional subspace method and uses constraint equations to link the nonlinear elements and biasing sources to the reduced order model. This approach significantly improves the simulation time of distributed nonlinear systems, since additional ports are not required to link the nonlinear elements to the reduced order model, yielding appreciable savings in the size of the reduced order model and computational time. 3. A parameterized reduction technique for nonlinear systems is presented. The proposed method uses multidimensional subspace and variational analysis to capture the variances of design parameters and approximates the weakly nonlinear functions as a Taylor series. An SVD approach is presented to address the efficiency of reduced order model. The proposed methodology significantly improves the simulation time of weakly nonlinear systems since the size of the reduced system is smaller than the original system and a new reduced model is not required each time a design parameter is changed

Electromagnetic Wave Theory and Applications

Contains table of contents for Section 3 and reports on seven research projects.Joint Services Electronics Program Contract DAAL03-89-C-0001National Science Foundation Contract ECS 86-20029Schlumberger- Doll ResearchU.S. Army Research Office Contract DAAL03 88-K-0057National Aeronautics and Space Administration Contract NAGW-1617U.S. Navy - Office of Naval Research Contract N00014-89-J-1107National Aeronautics and Space Administration Contract NAGW-1272National Aeronautics and Space Administration Contract 958461Simulation Technologies Contract DAAH01-87-C-0679U.S. Army Corp of Engineers Contract DACA39-87-K-0022WaveTracer, Inc.U.S. Navy - Office of Naval Research Contract N00014-89-J-1019U.S. Air Force Systems - Electronic Systems Division Contract F19628-88-K-0013Digital Equipment CorporationInternational Business Machines CorporationU.S. Department of Transportation Contract DTRS-57-88-C-0007

Performance assessment of multi-walled carbon nanotube interconnects using advanced polynomial chaos schemes

2019 Spring.Includes bibliographical references.With the continuous miniaturization in the latest VLSI technologies, manufacturing uncertainties at nanoscale processes and operations are unpredictable at the chip level, packaging level and at board levels of integrated systems. To overcome such issues, simulation solvers to model forward propagation of uncertainties or variations in random processes at the device level to the network response are required. Polynomial Chaos Expansion (PCE) of the random variables is the most common technique to model the unpredictability in the systems. Existing methods for uncertainty quantification have a major drawback that as the number of random variables in a system increases, its computational cost and time increases in a polynomial fashion. In order to alleviate the poor scalability of standard PC approaches, predictor-corrector polynomial chaos scheme and hyperbolic polynomial chaos expansion (HPCE) scheme are being proposed in this dissertation. In the predictor-corrector polynomial scheme, low-fidelity meta-model is generated using Equivalent Single Conductor (ESC) approximation model and then its accuracy is enhanced using low order multi-conductor circuit (MCC) model called a corrector model. In HPCE, sparser polynomial expansion is generated based on the hyperbolic criterion. These schemes result in an immense reduction in CPU cost and speed. This dissertation presents the novel approach to quantify the uncertainties in multi-walled carbon nano-tubes using these schemes. The accuracy and validation of these schemes are shown using various numerical examples