On the Systematic Synthesis of OTA-Based KHN Filters

According to the nullor-mirror descriptions of OTA, the NAM expansion method for three different types of KHN filters employing OTAs is considered. The type-A filters employing five OTAs have 32 different forms, the type-B filters employing four OTAs have 32 different forms, and the type-C filters employing three OTAs have eight different forms. At last a total of 72 circuits are received. Having used canonic number of components, the circuits are easy to be integrated and both pole frequency and Q-factor can be tuned electronically through tuning bias currents of the OTAs. The MULTISIM simulation results have been included to verify the workability of the derived circuit

Systematic Derivation for Quadrature Oscillators Using CCCCTAs

According to 16 nullor-mirror models of the current-controlled current conveyor transconductance amplifier (CCCCTA) and using nodal admittance matrix (NAM) expansion method, three different classes of the double-mode quadrature oscillators employed CCCCTAs and two grounded capacitors are synthesized. The class I oscillators have 32 different forms, the class II oscillators have 16 different forms, and the class III oscillators have four different forms. In all, 52 quadrature oscillators using CCCCTAs are obtained. Having used canonic number of components, the circuits are easy to be integrated and the condition for oscillation and the frequency of oscillation can be tuned by tuning bias currents of the CCCCTAs. The circuit analysis and simulation results have been included to support the generation method

Novel Floating General Element Simulators Using CBTA

In this study, a novel floating frequency dependent negative resistor (FDNR), floating inductor, floating capacitor and floating resistor simulator circuit employing two CBTAs and three passive components is proposed. The presented circuit can realize floating FDNR, inductor, capacitor or resistor depending on the passive component selection. Since the passive elements are all grounded, this circuit is suitable for fully integrated circuit design. The circuit does not require any component matching conditions, and it has a good sensitivity performance with respect to tracking errors. Moreover, the proposed FDNR, inductance, capacitor and resistor simulator can be tuned electronically by changing the biasing current of the CBTA or can be controlled through the grounded resistor or capacitor. The high-order frequency dependent element simulator circuit is also presented. Depending on the passive component selection, it realizes high-order floating circuit defining as V(s) = snAI(s) or V(s) = s-nBI(s). The proposed floating FDNR simulator circuit and floating high-order frequency dependent element simulator circuit are demonstrated by using PSPICE simulation for 0.25 μm, level 7, TSMC CMOS technology parameters

Deriving (MO)(I)CCCII Based Second-order Sinusoidal Oscillators with Non-interactive Tuning Laws using State Variable Method

The paper discusses systematic realization of second-order sinusoidal oscillators using multiple-output second-generation current controlled conveyor (MO-CCCII) and/or its inverting equivalent, namely the multiple-output inverting second-generation current controlled conveyor (MO-ICCCII) by state variable method. State variable method is a powerful technique and has been used extensively in the past to realize active RC oscillators using a variety of active building blocks (ABB). In this work, a noninteractive relationship between the condition of oscillation (CO) and the frequency of oscillation (FO) has been chosen priori and then state variable method is applied to derive the oscillators with grounded capacitors. All the resulting oscillator circuits, eight of them, are “resistor-less”, employ grounded capacitors and do not use more than three (MO)(I)CCCIIs. PSPICE simulation results of a possible CMOS implementation of the oscillators using 0:35μm TSMC CMOS technology parameters have validated their workability

Evaluation of output frequency responses of nonlinear systems under multiple inputs

In this paper, a new method for evaluating output frequency responses of nonlinear systems under multiple inputs, defined as a sum of sinusoids of different frequencies, is developed. The method circumvents difficulties associated with the existing “frequency-mix vector” based approaches and can easily be applied to investigate nonlinear behaviors of practical systems, including electronic circuits, at the system simulation and design stages. Application of the method to the analysis of nonlinear interference and distortion effects in communication receivers is studied, and specific procedures are proposed which can be directly used in practice for this analysi

Grounded capacitor-based new floating inductor simulators and a stability test

In this paper, two new floating inductor simulators (FISs), both using two differential difference current conveyors, are considered. The proposed FISs do not suffer from passive component matching constraints and employ a minimum number of passive elements. They use a grounded capacitor; accordingly, they are suitable for integrated circuit technology. They have good low- and high-frequency performances. Simulations are performed with the SPICE program to verify the claimed theory. Moreover, for the first FIS used in a second-order low-pass filter, a stability test is performed as an example. © TÜBITAK

Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization

This paper presents an extensive, non-exhaustive, study of available hard disk drive read channel equalization techniques used in the storage and readback of magnetically stored information. The physical elements and basic principles of the storage processes are introduced together with the basic theoretical definitions and models. Both read and write processes in magnetic storage are explained along with the definition of simple key concepts such as user bit density, intersymbol interference, linear and areal density, read head pulse response models, and coding algorithm