A Delta Debugger for ILP Query Execution

Because query execution is the most crucial part of Inductive Logic Programming (ILP) algorithms, a lot of effort is invested in developing faster execution mechanisms. These execution mechanisms typically have a low-level implementation, making them hard to debug. Moreover, other factors such as the complexity of the problems handled by ILP algorithms and size of the code base of ILP data mining systems make debugging at this level a very difficult job. In this work, we present the trace-based debugging approach currently used in the development of new execution mechanisms in hipP, the engine underlying the ACE Data Mining system. This debugger uses the delta debugging algorithm to automatically reduce the total time needed to expose bugs in ILP execution, thus making manual debugging step much lighter.Comment: Paper presented at the 16th Workshop on Logic-based Methods in Programming Environments (WLPE2006

Towards declarative diagnosis of constraint programs over finite domains

The paper proposes a theoretical approach of the debugging of constraint programs based on a notion of explanation tree. The proposed approach is an attempt to adapt algorithmic debugging to constraint programming. In this theoretical framework for domain reduction, explanations are proof trees explaining value removals. These proof trees are defined by inductive definitions which express the removals of values as consequences of other value removals. Explanations may be considered as the essence of constraint programming. They are a declarative view of the computation trace. The diagnosis consists in locating an error in an explanation rooted by a symptom.Comment: In M. Ronsse, K. De Bosschere (eds), proceedings of the Fifth International Workshop on Automated Debugging (AADEBUG 2003), September 2003, Ghent. cs.SE/030902

Towards a Generic Trace for Rule Based Constraint Reasoning

CHR is a very versatile programming language that allows programmers to declaratively specify constraint solvers. An important part of the development of such solvers is in their testing and debugging phases. Current CHR implementations support those phases by offering tracing facilities with limited information. In this report, we propose a new trace for CHR which contains enough information to analyze any aspects of \CHRv\ execution at some useful abstract level, common to several implementations. %a large family of rule based solvers. This approach is based on the idea of generic trace. Such a trace is formally defined as an extension of the $\omega_r^\lor$ semantics of CHR. We show that it can be derived form the SWI Prolog CHR trace

Debugging of Web Applications with Web-TLR

Web-TLR is a Web verification engine that is based on the well-established Rewriting Logic--Maude/LTLR tandem for Web system specification and model-checking. In Web-TLR, Web applications are expressed as rewrite theories that can be formally verified by using the Maude built-in LTLR model-checker. Whenever a property is refuted, a counterexample trace is delivered that reveals an undesired, erroneous navigation sequence. Unfortunately, the analysis (or even the simple inspection) of such counterexamples may be unfeasible because of the size and complexity of the traces under examination. In this paper, we endow Web-TLR with a new Web debugging facility that supports the efficient manipulation of counterexample traces. This facility is based on a backward trace-slicing technique for rewriting logic theories that allows the pieces of information that we are interested to be traced back through inverse rewrite sequences. The slicing process drastically simplifies the computation trace by dropping useless data that do not influence the final result. By using this facility, the Web engineer can focus on the relevant fragments of the failing application, which greatly reduces the manual debugging effort and also decreases the number of iterative verifications.Comment: In Proceedings WWV 2011, arXiv:1108.208

Automatic Detection of Performance Anomalies in Task-Parallel Programs

To efficiently exploit the resources of new many-core architectures, integrating dozens or even hundreds of cores per chip, parallel programming models have evolved to expose massive amounts of parallelism, often in the form of fine-grained tasks. Task-parallel languages, such as OpenStream, X10, Habanero Java and C or StarSs, simplify the development of applications for new architectures, but tuning task-parallel applications remains a major challenge. Performance bottlenecks can occur at any level of the implementation, from the algorithmic level (e.g., lack of parallelism or over-synchronization), to interactions with the operating and runtime systems (e.g., data placement on NUMA architectures), to inefficient use of the hardware (e.g., frequent cache misses or misaligned memory accesses); detecting such issues and determining the exact cause is a difficult task. In previous work, we developed Aftermath, an interactive tool for trace-based performance analysis and debugging of task-parallel programs and run-time systems. In contrast to other trace-based analysis tools, such as Paraver or Vampir, Aftermath offers native support for tasks, i.e., visualization, statistics and analysis tools adapted for performance debugging at task granularity. However, the tool currently does not provide support for the automatic detection of performance bottlenecks and it is up to the user to investigate the relevant aspects of program execution by focusing the inspection on specific slices of a trace file. In this paper, we present ongoing work on two extensions that guide the user through this process.Comment: Presented at 1st Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014) (arXiv:1405.2281

Enhancing Trace Debugging with Algorithmic and Omniscient Debugging

During many years, Print Debugging has been the most used method for debugging. Nowadays, however, industrial languages come with a trace debugger that allows programmers to trace computations step by step using breakpoints and state viewers. Almost all modern programming environments include a trace debugger that allows us to inspect the state of a computation in any given point. Nevertheless, this debugging method has been criticized for being completely manual and time-consuming. Other debugging techniques have appeared to solve some of the problems of Trace Debugging, but they suffer from other problems such as scalability. In this work we present a new hybrid debugging technique. It is based on a combination of Trace Debugging, Algorithmic Debugging and Omniscient Debugging to produce a synergy that exploits the best properties and strong points of each technique. We describe the architecture of our hybrid debugger and our implementation that has been integrated into Eclipse as a plugin.This work has been partially supported by the Spanish Ministerio de Economía y Competitividad (Secretaría de Estado de Investigación, Desarrollo e Innovación) under grant TIN2008-06622-C03-02 and by the Generalitat Valenciana under grant PROMETEO/2011/052. David Insa was partially supported by the Spanish Ministerio de Educación under FPU grant AP2010-4415.González, J.; Insa Cabrera, D.; Silva Galiana, JF. (2013). Enhancing Trace Debugging with Algorithmic and Omniscient Debugging. En Logic-Based Program Synthesis and Transformation. Springer. 183-201. http://hdl.handle.net/10251/72827S18320

A New Hybrid Debugging Architecture for Eclipse

The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-319-14125-1_11[EN] During many years, print debugging has been the most used method for debugging. Nowadays, however, industrial languages come with a trace debugger that allows programmers to trace computations step by step using breakpoints and state viewers. Almost all modern programming environments include a trace debugger that allows us to inspect the state of a computation in any given point. Nevertheless, this debugging method has been criticized for being completely manual and time-consuming. Other debugging techniques have appeared to solve some of the problems of Trace Debugging, but they suffer from other problems such as scalability. In this work we present a new hybrid debugging technique. It is based on a combination of Trace Debugging, Algorithmic Debugging and Omniscient Debugging to produce a synergy that exploits the best properties and strong points of each technique. We describe the architecture of our hybrid debugger and our implementation that has been integrated into Eclipse as a plugin.This work has been partially supported by the Spanish Ministerio de Economía y Competitividad (Secretaria de Estado de Investigación, Desarrollo e Innovación) under grant TIN2008-06622-003-02 and by the Generalitat Valenciana under grant PROMETEO/2011/052. David Insa was partially supported by the Spanish Ministerio de Educación under FPU grant AP2010-4415.González, J.; Insa Cabrera, D.; Silva Galiana, JF. (2013). A New Hybrid Debugging Architecture for Eclipse. En Logic-Based Program Synthesis and Transformation. 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Springer, Heidelberg (2003)Insa, D., Silva, J.: An Algorithmic Debugger for Java. In: Proceedings of the 26th IEEE International Conference on Software Maintenance (ICSM 2010), pp. 1–6 (2010)Insa, D., Silva, J.: Scaling Up Algorithmic Debugging with Virtual Execution Trees. In: Alpuente, M. (ed.) LOPSTR 2010. LNCS, vol. 6564, pp. 149–163. Springer, Heidelberg (2011)Insa, D., Silva, J.: loops2recursion Java Library (2013). http://www.dsic.upv.es/~jsilva/loops2recursion/Kouh, H.-J., Yoo, W.-H.: The Efficient Debugging System for Locating Logical Errors in Java Programs. In: Kumar, V., Gavrilova, M.L., Kenneth Tan, C.J., L’Ecuyer, P. (eds.) ICCSA 2003. LNCS, vol. 2667, pp. 684–693. Springer, Heidelberg (2003)B. Lewis. Debugging Backwards in Time. Available in the Computing Research Repository 2003, ( http://arxiv.org/abs/cs.SE/0310016 ), cs.SE/0310016Lienhard, A., Gîrba, T., Wang, J.: Practical Object-Oriented Back-in-Time Debugging. In: Vitek, J. (ed.) ECOOP 2008. LNCS, vol. 5142, pp. 592–615. Springer, Heidelberg (2008)S. Microsystems. Java Platform Debugger Architecture - JPDA (2010). http://java.sun.com/javase/technologies/core/toolsapis/jpda/Mirghasemi, S., Barton, J., Petitpierre, C.: Debugging by lastChange. Technical report (2011). http://people.epfl.ch/salman.mirghasemiNilsson, H.: Declarative Debugging for Lazy Functional Languages. PhD thesis, Linköping, Sweden (May 1998)Nilsson, H., Fritzson, P.: Algorithmic Debugging for Lazy Functional Languages. Journal of Functional Programming 4(3), 337–370 (1994)Pothier, G.: Towards Practical Omniscient Debugging. PhD thesis, University of Chile (June 2011)Shapiro, E.: Algorithmic Program Debugging. MIT Press (1982)Silva, J.: A Survey on Algorithmic Debugging Strategies. Advances in Engineering Software 42(11), 976–991 (2011

A Monitoring Language for Run Time and Post-Mortem Behavior Analysis and Visualization

UFO is a new implementation of FORMAN, a declarative monitoring language, in which rules are compiled into execution monitors that run on a virtual machine supported by the Alamo monitor architecture.Comment: In M. Ronsse, K. De Bosschere (eds), proceedings of the Fifth International Workshop on Automated Debugging (AADEBUG 2003), September 2003, Ghent. cs.SE/030902

A debugging environment for functional programming in CENTAUR

We present a trace-based debugging environment for a lazy functional language. We argue that traces are a natural even inevitable approach to debugging of lazy languages because stop-and-examine techniques run up against the unpredictability of lazy evaluation. We give a formal definition of trace describe how the Centaur system was used to build the environment and show our system being used to debug a small program. The more general goal of this work is to demonstrate a "hypertextual" approach to trace-based debugging. Our argument is that using hypertext techniques overcomes one of the most serious problems traditionally associated with traces : information overload

Efficient hardware debugging using parameterized FPGA reconfiguration

Functional errors and bugs inadvertently introduced at the RTL stage of the design process are responsible for the largest fraction of silicon IC re-spins. Thus, comprehensive func- tional verification is the key to reduce development costs and to deliver a product in time. The increasing demands for verification led to an increase in FPGA-based tools that perform emulation. These tools can run at much higher operating frequencies and achieve higher coverage than simulation. However, an important pitfall of the FPGA tools is that they suffer from limited internal signal observability, as only a small and preselected set of signals is guided towards (embedded) trace buffers and observed. This paper proposes a dynamically reconfigurable network of multiplexers that significantly enhance the visibility of internal signals. It allows the designer to dynamically change the small set of internal signals to be observed, virtually enlarging the set of observed signals significantly. These multiplexers occupy minimal space, as they are implemented by the FPGA’s routing infrastructure