Towards An Automated Approach to Hardware/Software Decomposition

We propose in this paper an algebraic approach to hard-ware/software partitioning in Verilog Hardware Description Language (HDL). We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog. Through this, we confirm successful verification for the correctness of the partitioning process by an algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.Singapore-MIT Alliance (SMA

A partition methodology to develop data flow dominated embedded systems

Comunicação apresentada no International Workshop on Model-Based Methodologies for Pervasive and Embedded Software (MOMPES 2004), 1, Hamilton, Ontario, Canada, 15-18 June 2004.This paper proposes an automatic partition methodology oriented to develop data flow dominated embedded systems. The target architecture is CPU-based with reconfigurable devices on attached board(s), which closely matches the PSM meta-model applied to system modelling. A PSM flow graph was developed to represent the system during the partitioning process. The partitioning task applies known optimization algorithms - tabu search and cluster growth algorithms - which were enriched with new elements to reduce computation time and to achieve higher quality partition solutions. These include the closeness function that guides cluster growth algorithm, which dynamically adapts to the type of object and partition under analysis. The methodology was applied to two case studies, and some evaluation results are presented

Implementing tuple space on transputer meshes

Research Report submitted to the Faculty of Science, University of the Witwatersrand, Johannesburg, towards a partial fulfilment of the requirements for the degree of Master of Science Johannesburg 1991This report describes and evaluates an implementation of the Linda tuple space abstraction on Transputer networks. There is evidence that suggests a need for a new programming methodology to support Transputer-based applications, and Linda, as an attractive and elegant alternative to existing methodologies, has great potential for this role. The research focuses on the implementation of a particular tuple space model, intermediate uniform distribution, on Transputer meshes. The objective of the research is to ascertain the extent of the communication overheads inherent in the implementation and hence evaluate the feasibility of the approach. The overheads are measured relative to message passing performance on native Transputer networks, and are shown to be significant. It is concluded that although the specific tuple space model is not ideally suited to Transputer-based systems and the implementation, as it stands, is too inefficient to be of practical use, the approach requires further exploration in order to exhaust its full research potential.MT201

High integrity hardware-software codesign

Programmable logic devices (PLDs) are increasing in complexity and speed, and are being used as important components in safety-critical systems. Methods for developing high-integrity software for these systems are well-known, but this is not true for programmable logic. We propose a process for developing a system incorporating software and PLDs, suitable for safety critical systems of the highest levels of integrity. This process incorporates the use of Synchronous Receptive Process Theory as a semantic basis for specifying and proving properties of programs executing on PLDs, and extends the use of SPARK Ada from a programming language for safety-critical systems software to cover the interface between software and programmable logic. We have validated this approach through the specification and development of a substantial safety-critical system incorporating both software and programmable logic components, and the development of tools to support this work. This enables us to claim that the methods demonstrated are not only feasible but also scale up to realistic system sizes, allowing development of such safety-critical software-hardware systems to the levels required by current system safety standards

Implementation and performance aspects of Kahn process networks : an investigation of problem modeling, implementation techniques, and scheduling strategies

For å spare strøm og redusere oppheting kjører moderne prosessorer på lavere frekvens enn de tidligere prosessorene. Produsentene kompenserer performansetapet ved å innpakke flere kjerner i en brikke som da kan kjøre flere programmer samtidig. Selv om prosessorer med flere kjerner har større total regnekraft enn de tidligere prosessorer, kjører likevel de fleste eksisterende programmer tregere enn på de eldre prosessorer. Dette skjer fordi programmer flest er skrevet på en måte som tillater dem å utnytte kun en av flere kjerner. For at et program skal kunne utnytte flere kjerner, må det omskrives nesten fra bunnen av, som er tidskrevende og dyrt. Ikke minst, utivklerne må lære en helt ny tankemåte. I dette arbeidet, som ble utført i perioden 2005-2009 ved Institutt for informatikk og Simula, har vi undersøkt hvordan vi kan gjøre det lettere å utvikle parallelle programmer som bruker flere kjerner. Vi tok utgangspunktet i det matematiske rammeverket av ”Kahn process networks”, som stammer fra 1970-tallet, og implementerte et bibliotek som gjør det mulig at eksisterende programmer kan lett utvides til å bruke flere kjerner. Med bruk av vårt bibliotek vil programmer automatisk kunne bruke alle tilgjengelige kjerner i en datamaskin, uten noen endringer. Våre eksperimenter har også vist at tilpasning av eksisterende programmer til vårt bibliotek krever minimale endringer i eksisterende kode

Task assignment in parallel processor systems

A generic object-oriented simulation platform is developed in order to conduct experiments on the performance of assignment schemes. The simulation platform, called Genesis, is generic in the sense that it can model the key parameters that describe a parallel system: the architecture, the program, the assignment scheme and the message routing strategy. Genesis uses as its basis a sound architectural representation scheme developed in the thesis. The thesis reports results from a number of experiments assessing the performance of assignment schemes using Genesis. The comparison results indicate that the new assignment scheme proposed in this thesis is a promising alternative to the work-greedy assignment schemes. The proposed scheme has a time-complexity less than those of the work-greedy schemes and achieves an average performance better than, or comparable to, those of the work-greedy schemes. To generate an assignment, some parameters describing the program model will be required. In many cases, accurate estimation of these parameters is hard. It is thought that inaccuracies in the estimation would lead to poor assignments. The thesis investigates this speculation and presents experimental evidence that shows such inaccuracies do not greatly affect the quality of the assignments