06141 Abstracts Collection -- Dynamically Reconfigurable Architectures

From 02.04.06 to 07.04.06, the Dagstuhl Seminar 06141 ``Dynamically Reconfigurable Architectures\u27\u27 was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available

Validation of quantum simulations: assessing efficiency and reliability in experimental implementations

Dissertação de mestrado em Engineering PhysicsQuantum simulation is one of the most relevant applications of quantum computation for the near future, due to its scientific impact and also because quantum simulation algorithms are typically less demanding than generalized quantum computations. Ultimately, the success of a quantum simulation depends on the amount and reliability of information one is able to extract from the results. In such a context, this work reviews the theory behind quantum simulation, with a focus on digital quantum simulation. The concepts of efficiency and reliability in quantum simulations are discussed, particularly for implementations of digital simulation algorithms in state-of-the-art quantum computers. A review of approaches for quantum characterization, verification and validation techniques (QCVV) is also presented. A digital quantum simulation of the Schrödinger equation for a single particle in 1 spatial dimension was experimentally implemented and analyzed, along with a quantum state tomography procedure for characterization of the final quantum state and evaluation of simulation reliability. From the literature, it is shown that digital quantum simulation is theoretically sound and experimentally feasible, with several applications in a wide range of physics-related fields. Nonetheless, a number of conditions arise that must be observed for a truly efficient implementation of a digital quantum simulation, from theoretical conception to experimental circuit design. The review of QCVV techniques highlights the need for characterization and validation techniques that could be efficiently implemented for current models of quantum computation, particularly in instances where classical verification is not tractable. However, there are proposals for efficient verification procedures when a set of parameters defining the final result of the simulation is known. The experimental simulation demonstrated partial success in comparison with an ideal quantum simulation. From the results it is apparent that better coherence times, better reliability and finer control are as decisive for the advancement of quantum computing power as the more-publicized number of qubits of a given device.A simulação quântica é uma das aplicações mais relevantes da computação quântica num futuro próximo, não só devido ao seu impacto científico como também porque os algoritmos de simulação quântica são tipicamente menos exigentes do que algoritmos quânticos numéricos. Em última análise, o sucesso de uma simulação quântica depende da quantidade e fiabilidade das informações que é possível extrair dos resultados. Neste contexto, este trabalho apresenta uma revisão da teoria da simulação quântica, com ênfase na simulação quântica digital. Os conceitos de eficiência e fiabilidade em simulações quânticas são discutidos, particularmente para implementações de algoritmos de simulação digital. Uma revisão de técnicas de caracterização, verificação e validação de sistemas quânticos (QCVV) é também apresentada. Uma simulação quântica digital da equação de Schrödinger para uma única partícula a uma dimensão espacial foi implementada experimentalmente e analisada, juntamente com um método de tomografia de estado quântico para a caracterização do estado quântico final e avaliação da fiabilidade da simulação. A partir da literatura, é demonstrado que a simulação quântica digital é teoricamente sólida e experimentalmente viável, com várias aplicações em diversas áreas da física. No entanto, existem várias condições a ter em conta para uma implementação verdadeiramente eficiente de uma simulação quântica digital, da sua concepção teórica até à implementação experimental de circuitos. A revisão de técnicas QCVV destaca a necessidade de técnicas de caracterização e validação que possam ser eficientemente implementadas para modelos atuais de computação quântica, particularmente em instâncias em que a verificação clássica não é possível ou desejável. No entanto, existem propostas para técnicas de verificação que são eficientes quando se conhece, a priori, um conjunto de parâmetros característicos do resultado final da simulação. A simulação experimental demonstrou sucesso parcial relativamente a uma simulação quântica ideal. A partir dos resultados, evidencia-se que melhores tempos de coerência, maior fiabilidade e controlo mais refinado são tão decisivos para o avanço da computação quântica quanto o número de qubits de um dispositivo

Cmos Backend Deposited Silicon Photonics - Material, Design, And Integration

Silicon photonics has the potential to enable continued scaling of computing performance by providing efficient high speed interconnects within and between logic processors, memory, and other peripherals, which are currently limited by fundamental limits of RF attenuation and spatial bandwidth density of electrical interconnects. However, the path to high performance, cost effective, and scalable integration of silicon photonics with CMOS microelectronic components has not been clear. In this dissertation, we present the vision of the Backend Deposited Silicon Photonics (BDSP) platform that can seamlessly integrate silicon photonics with CMOS microelectronics without disrupting the CMOS fabrication process. Every aspect of BDSP platform, including excimer laser annealed polycrystalline silicon, low loss silicon nitride waveguide, modulator, detector, electrical interface, backend CMOS compatibility, and 3D waveguide integration, is discussed in detail. We experimentally demonstrate key components of the backend deposited silicon photonics platform. We experimentally establish the post processing thermal budget limit for a 90 nm bulk CMOS process as 400? C for 90min. We then demonstrate fabrication of high quality passive polysilicon optical resonators with quality factors above 12,000 using excimer laser anneal. Building on this work, we demonstrate gigahertz electro-optic polysilicon modulator compatible with CMOS backend integration and also show photodetector operation. Optical resonators and waveguides monolithically integrated on CMOS and 3D integration of silicon nitride waveguide and polysilicon waveguide are also demonstrated. In addition, we demonstrate quasi-linear electro-optic phase modulation in silicon using optical mode and PN junction engineering. Finally, results are summarized and possible future works based on BDSP are discussed. This demonstration of the proposed backend deposited silicon photonics opens up a whole new horizon to silicon photonics integration on CMOS. By decoupling CMOS fabrication from photonics fabrication, we lower the barrier to introducing silicon photonics into CMOS foundries and potentially accelerate the adoption of silicon photonics

Design and Development of Smart Brain-Machine-Brain Interface (SBMIBI) for Deep Brain Stimulation and Other Biomedical Applications

Machine collaboration with the biological body/brain by sending electrical information back and forth is one of the leading research areas in neuro-engineering during the twenty-first century. Hence, Brain-Machine-Brain Interface (BMBI) is a powerful tool for achieving such machine-brain/body collaboration. BMBI generally is a smart device (usually invasive) that can record, store, and analyze neural activities, and generate corresponding responses in the form of electrical pulses to stimulate specific brain regions. The Smart Brain-Machine-Brain-Interface (SBMBI) is a step forward with compared to the traditional BMBI by including smart functions, such as in-electrode local computing capabilities, and availability of cloud connectivity in the system to take the advantage of powerful cloud computation in decision making. In this dissertation work, we designed and developed an innovative form of Smart Brain-Machine-Brain Interface (SBMBI) and studied its feasibility in different biomedical applications. With respect to power management, the SBMBI is a semi-passive platform. The communication module is fully passive—powered by RF harvested energy; whereas, the signal processing core is battery-assisted. The efficiency of the implemented RF energy harvester was measured to be 0.005%. One of potential applications of SBMBI is to configure a Smart Deep-Brain-Stimulator (SDBS) based on the general SBMBI platform. The SDBS consists of brain-implantable smart electrodes and a wireless-connected external controller. The SDBS electrodes operate as completely autonomous electronic implants that are capable of sensing and recording neural activities in real time, performing local processing, and generating arbitrary waveforms for neuro-stimulation. A bidirectional, secure, fully-passive wireless communication backbone was designed and integrated into this smart electrode to maintain contact between the smart electrodes and the controller. The standard EPC-Global protocol has been modified and adopted as the communication protocol in this design. The proposed SDBS, by using a SBMBI platform, was demonstrated and tested through a hardware prototype. Additionally the SBMBI was employed to develop a low-power wireless ECG data acquisition device. This device captures cardiac pulses through a non-invasive magnetic resonance electrode, processes the signal and sends it to the backend computer through the SBMBI interface. Analysis was performed to verify the integrity of received ECG data

Implantable Low-Noise Fiberless Optoelectrodes for Optogenetic Control of Distinct Neural Populations

The mammalian brain is often compared to an electrical circuit, and its dynamics and function are governed by communication across different types neurons. To treat neurological disorders like Alzheimer’s and Parkinson’s, which are characterized by inhibition or amplification of neural activity in a particular region or lack of communication between different regions of the brain, there is a need to understand troubleshoot neural networks at cellular or local circuit level. In this work, we introduce a novel implantable optoelectrode that can manipulate more than one neuron type at a single site, independently and simultaneously. By delivering multi-color light using a scalable optical waveguide mixer, we demonstrate manipulation of multiple neuron types at precise spatial locations in vivo for the first time. We report design, micro-fabrication and optoelectronic packaging of a fiber-less, multicolor optoelectrode. The compact optoelectrode design consists of a 7 μm x 30 μm dielectric optical waveguide mixer and eight electrical recording sites monolithically integrated on each shank of a 22 μm-thick four-shank silicon neural probe. The waveguide mixers are coupled to eight side-emitting injection laser diodes (ILDs) via gradient-index (GRIN) lenses assembled on the probe backend. GRIN-based optoelectrode enables efficient optical coupling with large alignment tolerance to provide wide optical power range (10 to 3000 mW/mm2 irradiance) at stimulation ports. It also keeps thermal dissipation and electromagnetic interference generated by light sources sufficiently far from the sensitive neural signals, allowing thermal and electrical noise management on a multilayer printed circuit board. We demonstrated device verification and validation in CA1 pyramidal layer of mice hippocampus in both anesthetized and awake animals. The packaged devices were used to manipulate variety of multi-opsin preparations in vivo expressing different combinations of Channelrhodopsin-2, Archaerhodopsin and ChrimsonR in pyramidal and parvalbumin interneuron cells. We show effective stimulation, inhibition and recording of neural spikes at precise spatial locations with less than 100 μV stimulation-locked transients on the recording channels, demonstrating novel use of this technology in the functional dissection of neural circuits.PHDBiomedical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137171/1/kkomal_1.pd

Full stack development toward a trapped ion logical qubit

Quantum error correction is a key step toward the construction of a large-scale quantum computer, by preventing small infidelities in quantum gates from accumulating over the course of an algorithm. Detecting and correcting errors is achieved by using multiple physical qubits to form a smaller number of robust logical qubits. The physical implementation of a logical qubit requires multiple qubits, on which high fidelity gates can be performed. The project aims to realize a logical qubit based on ions confined on a microfabricated surface trap. Each physical qubit will be a microwave dressed state qubit based on 171Yb+ ions. Gates are intended to be realized through RF and microwave radiation in combination with magnetic field gradients. The project vertically integrates software down to hardware compilation layers in order to deliver, in the near future, a fully functional small device demonstrator. This thesis presents novel results on multiple layers of a full stack quantum computer model. On the hardware level a robust quantum gate is studied and ion displacement over the X-junction geometry is demonstrated. The experimental organization is optimized through automation and compressed waveform data transmission. A new quantum assembly language purely dedicated to trapped ion quantum computers is introduced. The demonstrator is aimed at testing implementation of quantum error correction codes while preparing for larger scale iterations.Open Acces

Applications of Antenna Technology in Sensors

During the past few decades, information technologies have been evolving at a tremendous rate, causing profound changes to our world and to our ways of living. Emerging applications have opened u[ new routes and set new trends for antenna sensors. With the advent of the Internet of Things (IoT), the adaptation of antenna technologies for sensor and sensing applications has become more important. Now, the antennas must be reconfigurable, flexible, low profile, and low-cost, for applications from airborne and vehicles, to machine-to-machine, IoT, 5G, etc. This reprint aims to introduce and treat a series of advanced and emerging topics in the field of antenna sensors

Millimeter-wave interconnects for intra- and inter-chip transmission and beam steering in NoC-based multi-chip systems

The primary objective of this work is to investigate the communication capabilities of short-range millimeter-wave (mm-wave) communication among Network-on-Chip (NoC) based multi-core processors integrated on a substrate board. To address the demand for high-performance multi-chip computing systems, the present work studies the transmission coefficients between the on-chip antennas system for both intra- and inter-chip communication. It addresses techniques for enhancing transmission by using antenna arrays for beamforming. It also explores new and creative solutions to minimize the adverse effects of silicon on electromagnetic wave propagation using artificial magnetic conductors (AMC). The following summarizes the work performed and future work. Intra- and inter-chip transmission between wireless interconnects implemented as antennas on-chip (AoC), in a wire-bonded chip package are studied 30GHz and 60 GHz. The simulations are performed in ANSYS HFSS, which is based on the finite element method (FEM), to study the transmission and to analyze the electric field distribution. Simulation results have been validated with fabricated antennas at 30 GHz arranged in different orientations on silicon dies that can communicate with inter-chip transmission coefficients ranging from -45dB to -60dB while sustaining bandwidths up to 7GHz. The fabricated antennas show a shift in the resonant frequency to 25GHz. This shift is attributed to the Ground-Signal-Ground (GSG) probes used for measurement and to the Short-Open-Load (SOLT) calibration which has anomalies at millimeter-wave frequencies. Using measurements, a large-scale log-normal channel model is derived which can be used for system-level architecture design. Further, at 60 GHz densely packed multilayer copper wires in NoCs have been modeled to study their impact on the wireless transmission between antennas for both intra- and inter-chip links and are shown to be equivalent to copper sheets. It is seen that the antenna radiation efficiency reduces in the presence of these densely packed wires placed close to the antenna elements. Using this model, the reduction of inter-chip transmission is seen to be about 20dB as compared to a system with no wires. Lastly, the transmission characteristics of the antennas resonating at 60GHz in a flip-chip packaging environment are also presented

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast