Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

Hierarchical Agent-based Adaptation for Self-Aware Embedded Computing Systems

Siirretty Doriast

Application-specific thermal management of computer systems

Ph.DDOCTOR OF PHILOSOPH

Design of complex integrated systems based on networks-on-chip: Trading off performance, power and reliability

The steady advancement of microelectronics is associated with an escalating number of challenges for design engineers due to both the tiny dimensions and the enormous complexity of integrated systems. Against this background, this work deals with Network-On-Chip (NOC) as the emerging design paradigm to cope with diverse issues of nanotechnology. The detailed investigations within the chapters focus on the communication-centric aspects of multi-core-systems, whereas performance, power consumption as well as reliability are considered likewise as the essential design criteria

Space Transportation System and associated payloads: Glossary, acronyms, and abbreviations

A collection of acronyms now in everyday use in the Shuttle world are listed. It is a combination of lists that were prepared at the Kennedy and Johnson Space Centers and by the Air Force

Space transportation system and associated payloads: Glossary, acronyms, and abbreviations

A collection of some of the acronyms and abbreviations now in everyday use in the shuttle world is presented. It is a combination of lists that were prepared at Marshall Space Flight Center and Kennedy and Johnson Space Centers, places where intensive shuttle activities are being carried out. This list is intended as a guide or reference and should not be considered to have the status and sanction of a dictionary

Design of a smart power manager for digital communication systems

Portable devices, like mobile phones, are in an increasing need for power due to the growing complexity of applications and services provided by them. At the same time, mobile devices need to adapt their communication techniques so as to be able to work with different communication standards. The need for a multistandard communication circuit arises to overcome such a problem. Unfortunately, these circuits need to consume a considerable amount of power to achieve their designed goal. The researchers use the Dynamic Voltage / Frequency Scheduling technique to reduce power consumption in digital systems. This method employs the task time to schedule the system supply voltage along the task time to reduce the overall consumed power. Since the task time in digital communication systems is not defined, the application of the dynamic voltage/frequency technique on such systems is not possible. In this research, a closer look at the digital circuit power dissipation is given. Then, a new power model is introduced which can predict the digital circuit instantaneous power dissipation accurately. This model is used to build a power control strategy that makes use of the frequency as a control parameter. A setup is carried out using MATLAB to simulate the power of a NOT gate, a multiplexer circuit, a full adder and a two-bit full adder. The results are compared with OrCAD Cadence simulation for the same circuits. The results show that the new model can simulate the power dissipation accurately under different voltages, frequencies, and different technology sizes. In the second part of this research, a smart power manager is designed based on a fuzzy logic controller. The smart power manager makes use of the measured power and the input frequency to produce the required voltage to the digital system. The smart power manager is tested on a multiplexer circuit, two-bit full adder circuit, and cyclic redundancy check circuits. The results of the simulations show that the manager can reduce up to 60% of the consumed power by these circuits in low frequencies and up to 5% of the consumed power in high frequencies. The smart power manager can fulfil the purpose of the dynamic voltage/frequency scheduling technique without the need for the task time. In the final part of this research, the Long Term Evolution (LTE) system is taken as a case study. A unique cyclic redundancy check circuit is designed. This circuit is directed to work with LTE systems, so it has three generators integrated into it. The circuit can select the needed cyclic redundancy generator and produce the required remainder for the LTE system. The smart power manager is modified to supply both the voltage and frequency to the new cyclic redundancy check circuit so that it can control its consumed power. The selection of frequency depends on the used cyclic redundancy generator and the used modulation technique. The selected frequency ensures that the data rate between the LTE stages is constant. The results of the setup show that the smart power manager is capable of reducing the power of the circuit by more than 40% if it was operating at a constant frequency. The smart power manager can lower the power of the cyclic redundancy check circuit by more than 20% if the circuit is running under variable clock frequency. The conclusion driven from the results above proves that the SPM can reduce the consumed power in multi standard systems and Software Defined Radio (SDR) circuits

Hardware / Software Architectural and Technological Exploration for Energy-Efficient and Reliable Biomedical Devices

Nowadays, the ubiquity of smart appliances in our everyday lives is increasingly strengthening the links between humans and machines. Beyond making our lives easier and more convenient, smart devices are now playing an important role in personalized healthcare delivery. This technological breakthrough is particularly relevant in a world where population aging and unhealthy habits have made non-communicable diseases the first leading cause of death worldwide according to international public health organizations. In this context, smart health monitoring systems termed Wireless Body Sensor Nodes (WBSNs), represent a paradigm shift in the healthcare landscape by greatly lowering the cost of long-term monitoring of chronic diseases, as well as improving patients' lifestyles. WBSNs are able to autonomously acquire biological signals and embed on-node Digital Signal Processing (DSP) capabilities to deliver clinically-accurate health diagnoses in real-time, even outside of a hospital environment. Energy efficiency and reliability are fundamental requirements for WBSNs, since they must operate for extended periods of time, while relying on compact batteries. These constraints, in turn, impose carefully designed hardware and software architectures for hosting the execution of complex biomedical applications. In this thesis, I develop and explore novel solutions at the architectural and technological level of the integrated circuit design domain, to enhance the energy efficiency and reliability of current WBSNs. Firstly, following a top-down approach driven by the characteristics of biomedical algorithms, I perform an architectural exploration of a heterogeneous and reconfigurable computing platform devoted to bio-signal analysis. By interfacing a shared Coarse-Grained Reconfigurable Array (CGRA) accelerator, this domain-specific platform can achieve higher performance and energy savings, beyond the capabilities offered by a baseline multi-processor system. More precisely, I propose three CGRA architectures, each contributing differently to the maximization of the application parallelization. The proposed Single, Multi and Interleaved-Datapath CGRA designs allow the developed platform to achieve substantial energy savings of up to 37%, when executing complex biomedical applications, with respect to a multi-core-only platform. Secondly, I investigate how the modeling of technology reliability issues in logic and memory components can be exploited to adequately adjust the frequency and supply voltage of a circuit, with the aim of optimizing its computing performance and energy efficiency. To this end, I propose a novel framework for workload-dependent Bias Temperature Instability (BTI) impact analysis on biomedical application results quality. Remarkably, the framework is able to determine the range of safe circuit operating frequencies without introducing worst-case guard bands. Experiments highlight the possibility to safely raise the frequency up to 101% above the maximum obtained with the classical static timing analysis. Finally, through the study of several well-known biomedical algorithms, I propose an approach allowing energy savings by dynamically and unequally protecting an under-powered data memory in a new way compared to regular error protection schemes. This solution relies on the Dynamic eRror compEnsation And Masking (DREAM) technique that reduces by approximately 21% the energy consumed by traditional error correction codes