Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

Temperature Variation Aware Energy Optimization in Heterogeneous MPSoCs

Thermal effects are rapidly gaining importance in nanometer heterogeneous integrated systems. Increased power density, coupled with spatio-temporal variability of chip workload, cause lateral and vertical temperature non-uniformities (variations) in the chip structure. The assumption of an uniform temperature for a large circuit leads to inaccurate determination of key design parameters. To improve design quality, we need precise estimation of temperature at detailed spatial resolution which is very computationally intensive. Consequently, thermal analysis of the designs needs to be done at multiple levels of granularity. To further investigate the flow of chip/package thermal analysis we exploit the Intel Single Chip Cloud Computer (SCC) and propose a methodology for calibration of SCC on-die temperature sensors. We also develop an infrastructure for online monitoring of SCC temperature sensor readings and SCC power consumption. Having the thermal simulation tool in hand, we propose MiMAPT, an approach for analyzing delay, power and temperature in digital integrated circuits. MiMAPT integrates seamlessly into industrial Front-end and Back-end chip design flows. It accounts for temperature non-uniformities and self-heating while performing analysis. Furthermore, we extend the temperature variation aware analysis of designs to 3D MPSoCs with Wide-I/O DRAM. We improve the DRAM refresh power by considering the lateral and vertical temperature variations in the 3D structure and adapting the per-DRAM-bank refresh period accordingly. We develop an advanced virtual platform which models the performance, power, and thermal behavior of a 3D-integrated MPSoC with Wide-I/O DRAMs in detail. Moving towards real-world multi-core heterogeneous SoC designs, a reconfigurable heterogeneous platform (ZYNQ) is exploited to further study the performance and energy efficiency of various CPU-accelerator data sharing methods in heterogeneous hardware architectures. A complete hardware accelerator featuring clusters of OpenRISC CPUs, with dynamic address remapping capability is built and verified on a real hardware

Neural networks-on-chip for hybrid bio-electronic systems

PhD ThesisBy modelling the brains computation we can further our understanding of its function and develop novel treatments for neurological disorders. The brain is incredibly powerful and energy e cient, but its computation does not t well with the traditional computer architecture developed over the previous 70 years. Therefore, there is growing research focus in developing alternative computing technologies to enhance our neural modelling capability, with the expectation that the technology in itself will also bene t from increased awareness of neural computational paradigms. This thesis focuses upon developing a methodology to study the design of neural computing systems, with an emphasis on studying systems suitable for biomedical experiments. The methodology allows for the design to be optimized according to the application. For example, di erent case studies highlight how to reduce energy consumption, reduce silicon area, or to increase network throughput. High performance processing cores are presented for both Hodgkin-Huxley and Izhikevich neurons incorporating novel design features. Further, a complete energy/area model for a neural-network-on-chip is derived, which is used in two exemplar case-studies: a cortical neural circuit to benchmark typical system performance, illustrating how a 65,000 neuron network could be processed in real-time within a 100mW power budget; and a scalable highperformance processing platform for a cerebellar neural prosthesis. From these case-studies, the contribution of network granularity towards optimal neural-network-on-chip performance is explored

Méthodes de calcul numérique pour la simulation thermique des circuits intégrés

RÉSUMÉ La simulation thermique des circuits intégrés est aujourd'hui incontournable afin de prévenir les problèmes de dissipation thermique. Les circuits intégrés modernes exhibent une densité de puissance très élevée, pouvant conduire à une température excessive, dégradant les performances du circuit et réduisant sa durée de vie. Depuis leur invention en 1958, les circuits intégrés ont subi une évolution spectaculaire. La miniaturisation des composants, l'émergence des technologies tridimensionnelles et l'introduction de systèmes de refroidissement à base de liquide nécessitent de résoudre des problèmes thermiques très complexes. Les méthodes numériques fournissent un outil de simulation puissant, mais aussi très coûteux en calcul. Les simulateurs thermiques existants basés sur les méthodes numériques requièrent un temps d'exécution très long et une consommation de mémoire très importante. Ces inconvénients majeurs ralentissent considérablement la conception des circuits intégrés ou contraint à choisir des solutions thermiques non optimales. Cette thèse propose deux méthodes de calcul numérique originales pour accélérer la simulation thermique des circuits intégrés. La première méthode est destinée à la simulation du régime transitoire, tandis que la deuxième méthode cible le régime permanent. Les méthodes de calcul proposées combinent des algorithmes puissants tels que la décomposition des opérateurs, les méthodes de projection et la décomposition de domaine. Les méthodes de calcul proposées sont évaluées sur des problèmes thermiques réalistes et variés, en étant comparés à des méthodes de calcul classiques bien éprouvées. La méthodologie utilisée pour modéliser le comportement thermique des circuits intégrés est validée en comparant les résultats obtenus par simulation à des mesures thermiques effectuées sur un circuit physique réel. Dans le cadre de cette thèse, un simulateur thermique pour circuits intégrés, appelé ICTherm a été développé. Ce logiciel implémente les méthodes de calcul proposées dans cette thèse pour simuler le régime transitoire et le régime permanent. Le logiciel ICTherm est actuellement utilisé en milieu universitaire pour des projets de recherche.---------- ABSTRACT Since their introduction in 1958, integrated circuits have gone through a spectacular evolution. The transistor miniaturization, the emergence of tridimensional technologies have caused an explosion in complexity. In addition, modern integrated circuits generate very high heat fluxes that can lead to a high temperature, degrading the performance and reducing the lifetime of the device. The thermal simulation of integrated circuits is extensively used to prevent this kind of heat dissipation issues, but its application is becoming increasingly difficult with the growing complexity of chip designs. Numerical methods offer a powerful tool for the thermal simulation of integrated circuits. However, their high computation cost leads to long simulation times and to a vast memory usage, slowing down the design process or constraining the designer to unoptimized solutions. This thesis presents two highly-efficient methods for the thermal simulation of integrated circuits, for both transient and steady-state thermal problems. The proposed methods combine powerful algorithms, such as operator splitting, sub-space projection, and domain decomposition. We evaluated the proposed techniques on a variety of representative thermal problems. Our results show up to an order of magnitude improvement in simulation speed when compared against well established methods for the same level of accuracy. We have also validated our approach by comparing simulation results with the temperature measured on a physical device via infrared thermography, achieving an error smaller than 6%. In addition, we developed a thermal simulator for integrated circuits called ICTherm, implementing the methods proposed in this thesis. ICTherm can be used to simulate the transient and steady-state behaviour of arbitrary integrated circuits, and it is currently used for research by several universities

Caractérisation et modélisation d'interconnexions. Développement de nouvelles solutions pour la transmission d'informations au sein des cartes et puces électroniques.

Since the first IC in 1959 the performances and computing capacity of electronic devices have always grown, following thus the well-known empirical Moore’s law which says that the number of transistors in a dense integrated circuit doubles approximately every 18 months. This prevision is still verified even if some limitations appears like for example the limitation of the clock frequency which grow less than the projection that the ITRS (International Technology Roadmap for Semiconductors) has made in 2000. One of the stumbling point comes from interconnects which ensure the transmission of information inside electronic chips or cards. The interconnects imply delay, signal distortion, crosstalk and power dissipation and they now must be taken into account during electronic device design. So the researches depicted in this manuscript deal with the modelling of interconnect and study of new solutions to overcome problems due to classical interconnects. These works have been realized in Lab-STICC laboratory with the help of colleagues, post-doc, PhDs and Master Students. The manuscript include three chapters, the first one concerns researches on modelling aspects, the second is about alternative solutions to classical wired interconnects and to conclude the research projects for the next years are presented.The first chapter concern researches about modelling which aim to develop reliable models in view to simulate more quickly the electrical behavior of interconnects. Firstly the collaborations concerning the development of model-order reduction are presented. Then with the aim to evaluate the impact of inductive behavior, the current return patch problem and so the extraction of loop inductance is treated. The 3D discontinuities and 3D environment effects are presented in the third part of this chapter. For example the parallel grid influences on propagation are explored as well as the case of coupling between microvias and parallel-plates cavities inside multilayer PCB.The second chapter is about research of new solutions to overcome the limitation due to classical wired interconnects. A review of envisaged alternative solutions like for example optical interconnects and CNT (carbon Nano Tube) is first presented. Then a focus on RF guided interconnect is made and constraints in term of bandwidth are explained and some coupling techniques are explored. These studies naturally lead to exploration of the paradigm of wireless interconnects and the preliminary researches on radio transmission between two circuits placed on a PCB are shown. All these approaches of RF wireless interconnect are prelude to the research projects which are developed in a third chapter of the manuscript.The development of the draft over 4 years is based on the BBC project (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) funded by the Labex COMINLABS and which will begin in October 2016. The aims of this project are outlined as well as the aims of another project entitled “BROADWAYS” (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) which is currently in the second step of review by the ANR. To conclude this research part other embryonic researches are presented as well as long term researches envisaged like terahertz applications of the use of graphene for microwave applications.Depuis les premiers circuits intégrés en 1959 les composants et les systèmes électroniques n’ont cessé de voir leurs performances augmenter suivant ainsi la loi empirique de Gordon Moore qui prévoit un doublement de la complexité des circuits tous les 18 mois. Cette prévision reste aujourd’hui toujours vérifiée même si nous constatons depuis une dizaine d’années que les fréquences d’horloges stagnent autour de 4-5 GHz alors que l’ITRS (International Technology Roadmap for Semiconductors) prévoyait dans les années 2000 des fréquences de travail pouvant atteindre 40 GHz pour 2016. L’un des facteurs limitant la progression des performances vient des interconnexions métalliques servant au transport de l’information au sein des systèmes électroniques. Les travaux de recherche présentés dans le cadre de l’obtention de l‘habilitation à diriger des recherches concernent d’une part les travaux réalisés sur la modélisation des interconnexions et d’autre part ceux sur l’étude de solutions alternatives à ces interconnexions classiques. Ces travaux ont été réalisés au sein du Lab-STICC en collaboration avec plusieurs collègues et lors de l’encadrement de plusieurs post-doctorants, doctorants et stagiaires de master recherche. Le mémoire comporte trois chapitres principaux, le premier concerne les travaux sur la modélisation des interconnexions, le second porte sur l’étude de solutions alternatives à ces interconnexions classiques et le dernier permet la présentation des projets de recherches pour les prochaines années.L’objectif de nos travaux sur la modélisation des interconnexions consiste au développement de modèles fiables permettant d’appréhender leurs effets sur les signaux. Dans un premier temps, les travaux portant sur l’obtention de modèles à complexité réduite sont présentés. Puis, afin d’évaluer l’impact des effets inductifs des interconnexions, nous présentons les travaux sur l’identification des chemins de retours du courant dans un réseau comprenant plusieurs lignes et qui sont nécessaires pour déterminer les inductances de boucles. La prise en compte de l’environnement 3D des interconnexions fait l’objet de la troisième partie de ce chapitre. Nous traitons ainsi de l’influence de différentes discontinuités et nous présentons des règles de design permettant la limitation des risques de conversion de mode de propagation. Dans le cadre de structures multicouches, nous abordons l’influence de grilles métalliques placées au voisinage d’une ligne sur la propagation des signaux. Enfin nous traitons des risques de couplage entre des vias et les modes de cavités au sein des structures PCB multicouches.La seconde thématique développée dans ce mémoire porte sur le développement de solutions alternatives aux interconnexions classiques. Après avoir listé certaines de ces solutions telle que les interconnexions optiques ou les nanotubes de carbone, nous présentons plus particulièrement les interconnexions RF qui véhiculent l’information numérique sur porteuse à haute fréquence. Dans un premier temps nous analysons les interconnexions RF guidées qui utilisent une ligne de transmission comme support pour transporter l’information. A partir de l’étude des modes d’accès multiples nous montrons que les canaux doivent être large bande et nous explorons diverses façons de transmettre l’énergie à la ligne de transmission. Enfin nous présentons quelques exemples de performances obtenues à l’aide de démonstrateurs numériques. Ces études des interconnexions RF guidées nous ont naturellement amené à considérer les possibilités de transmission par voie hertzienne des informations au sein des cartes et puces électroniques. Nous avons ainsi analysé à l’aide de démonstrateurs très simples les niveaux de transmission entre deux circuits placés sur une même carte PCB (Printed Circuit Board).Ces études initiales sur les interconnexions radios ou sans fils servent de point d’appui aux projets de recherche présentés à la fin de ce manuscrit. La philosophie du projet BBC (wireless interconnect network on chip or in board for Broadcast-Based parallel Computing) financé par le Labex COMINLABS à partir d’octobre est présenté de même que celle du projet ANR Broadways (Broadcast-Based new paradigms of ubiquitous memory mapping, bandwidth allocation and parallel programing made possible by Radio Network On Chip) en seconde phase d’étude auprès de l’ANR

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip

High temperature is one of the limiting factors and major concerns in 3D-chip integration. In this paper we use a 3D test chip (WIDEIO DRAM on top of a logic die) equipped with temperature sensors and heaters to explore thermal effects. We correlated real temperature measurements with the power dissipated by the heaters using model learning techniques. The resulting compact thermal model is able to predict temperatures at chip locations far from the temperature sensors and to infer the power dissipation at any location of the chip. Results are verified by mean of an off-sample validation technique and show a high accuracy of the compact thermal model when compared with silicon measurements