A Classification and Survey of Computer System Performance Evaluation Techniques

Classification and survey of computer system performance evaluation technique

On-Line Computing With a Hierarchy of Processors

Time shared computer systems have been based upon the two techniques of multiprogramming and swapping. Multiprogramming is based on restricting each program to a portion of the total computer memory. Swapping requires considerable overhead time for loading and unloading programs. To alleviate the size restriction due to multiprogramming, segmentation is employed, resulting in fact in vastly increased swapping. A new system architecture is proposed for time shared computing that alleviates the high overhead or program size restriction. It utilizes a hierarchy of processors, where each processor is assigned tasks on the basis of four factors: interactive requirements, frequency of use, execution time, and program length. In order to study the hierarchical approach to system architecture, the Moore School Problem Solving Facility (MSPSF) was built and used. The study of the manner of operation and the reactions of the users clarified and defined the Hierarchy of Processors system architecture. The Moore School Problem Solving Facility was implemented on second generation equipment, the IBM 7040, and therefore it is not possible to adequately compare the efficiency with third generation computers operating in a swapping mode. The conclusions of this dissertation center around the methodology of designing such a system, including the specification of facilities for each level of the hierarchy. Six major conclusions are given: (1) Three processors in the hierarchy have been necessary, but it is conceivable that more may be employed in other future situations. (2) Each of the processors in the hierarchy should be general purpose. (3) Program compatibility between the processors is necessary. (4) The assigning of tasks to the processors within the system should be optionally user directed or automatic. Similarly, if a task exceeds the resources of the processor to which it has been assigned, redirection should be possible either automatically or by the user. (5) A macro language is necessary between every pair of processors for effective communication. Such a language processor, IXSYS, has been constructed and its use is described in detail in the dissertation, demonstrating the need and utility. (6) In addition to the three hierarchical processors, a separate processor may be advantageously used for storage, retrieval and management of information in files. Such a processor should be directly accessible from each of the other processors

Analysis of some algorithms for use on paged virtual memory computers

PhD ThesisHandling a single page fault involves execution of thousands of instructions, drum rotational delay and is usually so expensive that if it can be avoided, almost any other cost can be tolerated. Optimizing operating system performance is usually the main concern of computer seientists who deal with paged memories. However, redesigning the algorithm used by a problem program can often result in a very significant reduction in paging, and hence in program execution time. The redesigned algorithm frequently does not satisfy the more conventional efficiency criteria. A sorting algorithm, Hash Coding and other search algorithms are considered. Analytic and simulation studies are presented, and aome modifications are proposed to reduce the number of page faults produced by data set references. Analysis is in terms of three of the most commonly used page replacement algorithms i.e. least recently used, first in first out, and random selection. The modifications are for the most part relatively minor and in some cases have appeared elsewhere in the context of searching on external storage media. The important aspects are the dramatic performance improvements which are possible, and the fact that classical internal algorithms are inappropriate for use in a paged virtual memory system.The Science Research Council: The University of Newcastle Upon Tyne: International Business Machines (United Kingdom) Limited.

A simulation model of the control data 6400 scope operating system

This thesis describes a simulation model for the CDC 6400 computer system under the SCOPE 3.3 Operating System

The analysis and simulation of multi-access computer systems

Digitisation of this thesis was sponsored by Arcadia Fund, a charitable fund of Lisbet Rausing and Peter Baldwin

SIMULATION OF A MULTIPROCESSOR COMPUTER SYSTEM

The introduction of computers and software engineering in telephone switching systems has dictated the need for powerful design aids for such complex systems. Among these design aids simulators - real-time environment simulators and flat-level simulators - have been found particularly useful in stored program controlled switching systems design and evaluation. However, both types of simulators suffer from certain disadvantages. An alternative methodology to the simulation of stored program controlled switching systems is proposed in this research. The methodology is based on the development of a process-based multilevel hierarchically structured software simulator. This methodology eliminates the disadvantages of environment and flat-level simulators. It enables the modelling of the system in a 1 to 1 transformation process retaining the sub-systems interfaces and, hence, making it easier to see the resemblance between the model and modelled system and to incorporate design modifications and/or additions in the simulator. This methodology has been applied in building a simulation package for the System X family of exchanges. The Processor Utility Sub-system used to control the exchanges is first simulated, verified and validated. The application sub-systems models are then added one level higher_, resulting in an open-ended simulator having sub-systems models at different levels of detail and capable of simulating any member of the System X family of exchanges. The viability of the methodology is demonstrated by conducting experiments to tune the real-time operating system and by simulating a particular exchange - The Digital Main Network Switching Centre - in order to determine its performance characteristics.The General Electric Company Ltd, GEC Hirst Research Cent, Wemble