Multi-level analysis of on-chip optical wireless links

Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of \u3bcm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip

Multi-level analysis of on-chip optical wireless links

Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of μm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip

The Impact of LSI (Large Scale Integration) on System Packaging

System packaging of LSI circuit

Thermo-mechanical analysis of flexible and stretchable systems

This paper presents a summary of the modeling and technology developed for flexible and stretchable electronics. The integration of ultra thin dies at package level, with thickness in the range of 20 to 30 μ m, into flexible and/or stretchable materials are demonstrated as well as the design and reliability test of stretchable metal interconnections at board level are analyzed by both experiments and finite element modeling. These technologies can achieve mechanically bendable and stretchable subsystems. The base substrate used for the fabrication of flexible circuits is a uniform polyimide layer, while silicones materials are preferred for the stretchable circuits. The method developed for chip embedding and interconnections is named Ultra Thin Chip Package (UTCP). Extensions of this technology can be achieved by stacking and embedding thin dies in polyimide, providing large benefits in electrical performance and still allowing some mechanical flexibility. These flexible circuits can be converted into stretchable circuits by replacing the relatively rigid polyimide by a soft and elastic silicone material. We have shown through finite element modeling and experimental validation that an appropriate thermo mechanical design is necessary to achieve mechanically reliable circuits and thermally optimized packages

Two- and Three-dimensional High Performance, Patterned Overlay Multi-chip Module Technology

A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage

Low-cost technology for the integration of micro- and nanochips into fluidic systems on printed circuit board: fabrication challenges

Nowadays, micro- and nanochips are usually\ud fabricated with Silicon and/or glass. A simple, low-cost and\ud reliable integration packaging method that provides flexibility\ud to the incorporation of electronic and fluidic devices into a\ud system has not been fully developed yet. The use of Printed\ud Circuit Board material as substrate to create dry film resist\ud microfluidic channels is the core technology to provide such an\ud integration method. The feasibility and potential of the\ud proposed packaging method is demonstrated in this wor

Scalability of Optical Interconnects Based on Microring Resonators

This letter investigates the use of optical microring resonators as switching elements (SEs) in large optical interconnection fabrics. We introduce a simple physical-layer model to assess scalability in crossbar- and Benes-based architectures.We also propose a new dilated SE that improves scalability to build fabrics of several terabits per second of aggregate capacit