A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Performance optimization of lateral-mode thin-film piezoelectric-on-substrate resonant systems

The main focus of this dissertation is to characterize and improve the performance of thin-film piezoelectric-on-substrate (TPoS) lateral-mode resonators and filters. TPoS is a class of piezoelectric MEMS devices which benefits from the high coupling coefficient of the piezoelectric transduction mechanism while taking advantage of superior acoustic properties of a substrate. The use of lateral-mode TPoS designs allows for fabrication of dispersed-frequency filters on a single substrate, thus significantly reducing the size and manufacturing cost of devices. TPoS filters also offer a lower temperature coefficient of frequency, and better power handling capability compared to rival technologies all in a very small footprint. Design and fabrication process of the TPoS devices is discussed. Both silicon and diamond substrates are utilized for fabrication of TPoS devices and results are compared. Specifically, the superior acoustic properties of nanocrystalline diamond in scaling the frequency and energy density of the resonators is highlighted in comparison with silicon. The performance of TPoS devices in a variety of applications is reported. These applications include lateral-mode TPoS filters with record low IL values (as low as 2dB) and fractional bandwidth up to 1%, impedance transformers, very low phase noise oscillators, and passive wireless temperature sensors

Gallium Nitride Integrated Microsystems for Radio Frequency Applications.

The focus of this work is design, fabrication, and characterization of novel and advanced electro-acoustic devices and integrated micro/nano systems based on Gallium Nitride (GaN). Looking beyond silicon (Si), compound semiconductors, such as GaN have significantly improved the performance of the existing electronic devices, as well as enabled completely novel micro/nano systems. GaN is of particular interest in the “More than Moore” era because it combines the advantages of a wide-band gap semiconductor with strong piezoelectric properties. Popular in optoelectronics, high-power and high-frequency applications, the added piezoelectric feature, extends the research horizons of GaN to diverse scientific and multi-disciplinary fields. In this work, we have incorporated GaN micro-electro-mechanical systems (MEMS) and acoustic resonators to the GaN baseline process and used high electron mobility transistors (HEMTs) to actuate, sense and amplify the acoustic waves based on depletion, piezoelectric, thermal and piezo-resistive mechanisms and achieved resonance frequencies ranging from 100s of MHz up to 10 GHz with frequency×quality factor (f×Q) values as high as 1013. Such high-performance integrated systems can be utilized in radio frequency (RF) and microwave communication and extreme-environment applications.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/135799/1/azadans_1.pd

Amplifier Design for a Pipeline ADC in 90nm Technology

This paper explains the choices taken for the design of two full differential operational amplifiers. These op amp have been designed for the third and the fifth stage of a pipelined A/D Converter. It shows also the solutions found to reach high gain, wide bandwidth and short settling time, without degrading too much the output swing. First the operational amplifier specification are extracted starting from the ADC architecture, then the issues related to the sub-micrometrical design are analysed; the different structures tested are then presented and the motivation of the final topology choice are shown. It presents then the op amp schematic implementation, the simulation results and the layout with the 90nm TSMC design ki

Micromachines for Dielectrophoresis

An outstanding compilation that reflects the state-of-the art on Dielectrophoresis (DEP) in 2020. Contributions include: - A novel mathematical framework to analyze particle dynamics inside a circular arc microchannel using computational modeling. - A fundamental study of the passive focusing of particles in ratchet microchannels using direct-current DEP. - A novel molecular version of the Clausius-Mossotti factor that bridges the gap between theory and experiments in DEP of proteins. - The use of titanium electrodes to rapidly enrich T. brucei parasites towards a diagnostic assay. - Leveraging induced-charge electrophoresis (ICEP) to control the direction and speed of Janus particles. - An integrated device for the isolation, retrieval, and off-chip recovery of single cells. - Feasibility of using well-established CMOS processes to fabricate DEP devices. - The use of an exponential function to drive electrowetting displays to reduce flicker and improve the static display performance. - A novel waveform to drive electrophoretic displays with improved display quality and reduced flicker intensity. - Review of how combining electrode structures, single or multiple field magnitudes and/or frequencies, as well as variations in the media suspending the particles can improve the sensitivity of DEP-based particle separations. - Improvement of dielectrophoretic particle chromatography (DPC) of latex particles by exploiting differences in both their DEP mobility and their crossover frequencies

Doctor of Philosophy

dissertationTactile sensors are a group of sensors that are widely being developed for transduction of touch, force and pressure in the field of robotics, contact sensing and gait analysis. These sensors are employed to measure and register interactions between contact surfaces and the surrounding environment. Since these sensors have gained usage in the field of robotics and gait analysis, there is a need for these sensors to be ultra flexible, highly reliable and capable of measuring pressure and two-axial shear simultaneously. The sensors that are currently available are not capable of achieving all the aforementioned qualities. The goal of this work is to design and develop such a flexible tactile sensor array based on a capacitive sensing scheme and we call it the flexible tactile imager (FTI). The developed design can be easily multiplexed into a high-density array of 676 multi-fingered capacitors that are capable of measuring pressure and two-axial shear simultaneously while maintaining sensor flexibility and reliability. The sensitivity of normal and shear stress for the FTI are 0.74/MPa and 79.5/GPa, respectively, and the resolvable displacement and velocity are as low as 60 µm and 100 µm/s, respectively. The developed FTI demonstrates the ability to detect pressure and shear contours of objects rolling on top of it and capability to measure microdisplacement and microvelocities that are desirable during gait analysis

Characterization of process variability and robust optimization of analog circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 161-174).Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm CMOS technologies, providing advantages in cost and high density integration compared to other heterogeneous technologies such as SiGe and III-V compound semiconductors. However, as the operating frequency of CMOS circuits increases, it becomes more difficult to obtain sufficiently wide operating ranges for robust operation in essential analog building blocks such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by the random and systematic variations in key manufacturing steps become more significant in nano-scale technologies. The process variation of circuit performance is quickly becoming one of the main concerns in high performance analog design. In this thesis, we show design and analysis of a VCO and frequency divider operating beyond 70GHz in a 65nm SOI CMOS technology. The VCO and frequency divider employ design techniques enlarging frequency operating ranges to improve the robustness of circuit operation. Circuit performance is measured from a number of die samples to identify the statistical properties of performance variation. A back-propagation of variation (BPV) scheme based on sensitivity analysis of circuit performance is proposed to extract critical circuit parameter variation using statistical measurement results of the frequency divider. We analyze functional failure caused by performance variability, and propose dynamic and static optimization methods to improve parametric yield. An external bias control is utilized to dynamically tune the divider operating range and to compensate for performance variation. A novel time delay model of a differential CML buffer is proposed to functionally approximate the maximum operating frequency of the frequency divider, which dramatically reduces computational cost of parametric yield estimation. The functional approximation enables the optimization of the VCO and frequency divider parametric yield with a reasonable amount of simulation time.by Daihyun Lim.Ph.D

Above-IC RF MEMS devices for communication applications

Wireless communications are showing an explosive growth in emerging consumer and military applications of radiofrequency (RF), microwave, and millimeter-wave circuits and systems. Applications include wireless personal connectivity (Bluetooth), wireless local area networks (WLAN), mobile communication systems (GSM, GPRS, UMTS, CDMA), satellite communications and automotive electronics. Future cell phones and ground communication systems as well as communication satellites will require more and more sophisticated technologies. The increasing demand for size and weight reduction, cost savings, low power consumption, increased frequency and higher functionality and reconfigurability as part of multiband and multistandard operation is necessitating the use of highly integrated RF front-end circuits. Chip scaling has made a major contribution to this goal, but today a situation has been reached where the presence of numerous off-chip passive RF components imposes a critical bottleneck to further integration and miniaturization of wireless transceivers. Microelectromechanical systems (MEMS) technology is a rapidly emerging enabling technology that is intended to replace the discrete passives by their integrated counterparts. In this thesis, an original metal surface micromachining process, which is compatible with CMOS post-processing, for above-IC integration of RF MEMS tunable capacitors and suspended inductors is presented. A detailed study on SF6 inductively coupled plasma (ICP) releasing has been performed in order to ascertain the optimal process parameters. This study has emphasized the fact that temperature plays an important role in this process by limiting silicon dioxide etching. Moreover, the optimized recipe has been found to be independent of the sacrificial layer used (amorphous or polycrystalline silicon) and its thickness. Using this recipe, 15.6 µm/min Si underetch rate with high Si: SiO2 selectivity (> 20000: 1) has been obtained. Single-air-gap and double-air-gap parallel-plate MEMS tunable capacitors have been designed, fabricated and characterized in the pF range, from 1 MHz to 13.5 GHz. It has been shown that an optimized design of the suspended membrane and direct symmetrical current feed at both ports can significantly improve the quality factor and increase the self-resonant frequency, pushing it to 12 GHz and beyond. The maximum capacitance tuning range obtained for a single-air-gap capacitor is 29% for a bias voltage of 20 V. The maximum capacitance tuning range obtained for a double-air-gap capacitor is 207% for a bias voltage of 70 V. The post-processing of X-FAB BiCMOS wafers has been successfully demonstrated to fabricate monolithically integrated VCOs with above-IC MEMS LC tank. Comparing a suspended inductor and the X-FAB inductor with the same design, it has been shown that increasing the thickness of the spiral from 2.3 to 4 µm and having the spiral suspended 3 µm above the passivation layers lead to an improvement factor of 2 for the peak quality factor and a shift of the self-resonant frequency beyond 15 GHz. No significant variation on bipolar and MOS transistors characteristics due to the post-processing has been observed and we conclude that the variation due to post-processing is in the same range as the wafer-to-wafer variation. Based on our metal surface micromachining process, coplanar waveguide (CPW) MEMS shunt capacitive switches and variable true-time delay lines (V-TTDLs) have been designed, fabricated and characterized in the 1 - 20 GHz range. A novel MEMS device architecture: the SG-MOSFET, which combines a solid-state MOS transistor and a metal suspended gate has been proposed as DC current switch. The corresponding fabrication process using polysilicon as a sacrificial layer has been developed to release metal gate suspended over gate oxide by SF6 plasma. Very abrupt current switches have been demonstrated with subthreshold slope better than 10 mV/decade (better than the theoretical solid-state bulk or SOI MOSFET limit of 60 mV/decade) and ultra-low gate leakage (less than 0.001 pA/µm2) due to the air-gap