The Effect of Design Parameters on Single-Event Upset Sensitivity of MOS Current Mode Logic

In this paper, we describe and discuss the effects of design parameters such as transistor size, output voltage swing and bias current on radiation sensitivity of MOS current mode logic (MCML) type sequential elements that are used in high-speed communication systems. We have implemented latches and flipflops in 90 nm technology and show how single-event upset can be mitigated just by adjusting particular design factors at the same clock frequency. It is shown that the critical charge needed to upset the logic state of a sequential element increases up to 5 times by increasing the bias current at the cost of more power and up to 2 times by increasing output voltage swing at the cost of more area. The effect of changing operation frequency from 500MHz to 4GHz on single-event upset is also investigated. For frequencies higher than 2 GHz, critical charge improves 1.3 times. Also in mixed-signal environments, CMOS causes crosstalk between analog and digital circuitry [3]. Recently, moving to very high speed systems and integrating analog and digital circuitry onto the same die has drawn attentio