A Real-time Network Emulator: ADLARS Case Study

As testing and benchmarking performance of web services and networked applications has proven to be cost-effective, and crucial in some applications, increased significance has been attached to the development of hardware and software network emulators and simulators. In this paper, we discuss a possible design of a light-w eight real-time IP network emulator that can provide the same functionality and performance as hardware simulators. Also, as the systematic software engineering discipline has become a necessity in the software development life-cycle, we present a possible approach, utilizing mature software engineering disciplines, for building the software architecture of the emulator. We then use ADLARS [1], an A rchitecture D escription Language for Real-time Systems developed within our research team to describe the architecture. The emulator’s architecture serves as a good test-bed for our ADL because of its real-time and concurrent nature. We conclude by testing our design and presenting a possible JAVA instantiation of the emulator over a UNIX system

Case Study: Using ADLARS to Design and Develop a Real-Time Network Emulator

As testing and benchmarking performance of web services and networked applications has proven to be cost-effective, and crucial in some applications, increased significance has been attached to the development of hardware and software network emulators and simulators. In this paper, we discuss a possible design of a light-weight real-time IP network emulator that can provide the same functionality and performance as hardware simulators. Also, as the systematic software engineering discipline has become a necessity in the software development life-cycle, we present a possible approach, utilizing mature software engineering disciplines, for building the software architecture of the emulator. We then use ADLARS [1], an Architecture Description Language for Real-time Systems to describe the architecture. The emulator’s architecture serves as a good test-bed for our ADL because of its real-time and concurrent nature. We conclude by testing our design and presenting a possible JAVA implementation of the emulator over a UNIX system

Automated channel emulator based on MEMS switch and improvement of signal transition

Channel Emulator, which is widely used in communication system development, is an instrument that emulates the real-world signal propagation environment between transmitter and. [sic] To overcome the disadvantages of traditional channel emulator, we propose a novel structure of the automated channel emulator in Section 1, which can be controlled by software and integrated into auto-testing system. MEMS switch, with good RF performance, is used to connect and isolate multiple channels. In Section 2, we divide the whole channel emulator system into Channel, Support, and Controller Board, and provide detailed design procedures with critical parameters of each board. The well-designed high frequency channel traces are validated by both 2D/3D simulation models and analytical calculations. The automated control logic and driven mechanism are also illustrated by sequence and block diagram. In Section 3, we perform post-simulation after the completion of PCB layout to check the RF performance of the real PCB board. Then manufacture and assemble the whole system of the automated channel emulator. In Section 4, we study the discontinuities in channel path in a systematically approach, including: channel trace turns, connector transient tapering, wire-bonding and solder parasitic effects. Analysis, simulations and measurements are performed to provide improvement solutions of signal transition. Section 5 concludes this thesis work and discuss about the future plan to expand our channel emulator design to differential solution --Abstract, page iii

A heterogeneous computer vision architecture: implementation issues

The prototype of a heterogeneous architecture is currently being built. The architecture is aimed at video-rate computing and is based on a message passing MIMD topology at the top level-transputer based-and on VLSI associative processor arrays (APA, SIMD structure) for low level image processing tasks. The APA structure is implemented through a set of 4 VLSI chips (GLiTCH) containing 64 1-bit processing elements each. This communication addresses some issues concerning the implementation of the first prototype, namely those related to: • the design and integration of the APA controller unit, which provides the required interface between the APA, the MIMD topology and the video image interface: • the evaluation of the GLiTCH chip through an emulator based on transputers and fast programmable devices; the emulator was designed to be flexible enough to evaluate later modifications to the GLiTCH design; • the design of an integrated set of software development tools containing a structured editor-syntax oriented, with a visual interface/programming interface-and a cross compiler and debugger

PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems

We have developed PGPG (Pipeline Generator for Programmable GRAPE), a software which generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs). An FBCE typically consists of one or multiple FPGA (Field-Programmable Gate Array) chips and local memory. Here, the term "Field-Programmable" means that one can rewrite the logic implemented to the chip after the hardware is completed, and therefore a single FBCE can be used for calculation of various functions, for example pipeline processors for gravity, SPH interaction, or image processing. The main problem with FBCEs is that the user need to develop the detailed hardware design for the processor to be implemented to FPGA chips. In addition, she or he has to write the control logic for the processor, communication and data conversion library on the host processor, and application program which uses the developed processor. These require detailed knowledge of hardware design, a hardware description language such as VHDL, the operating system and the application, and amount of human work is huge. A relatively simple design would require 1 person-year or more. The PGPG software generates all necessary design descriptions, except for the application software itself, from a high-level design description of the pipeline processor in the PGPG language. The PGPG language is a simple language, specialized to the description of pipeline processors. Thus, the design of pipeline processor in PGPG language is much easier than the traditional design. For real applications such as the pipeline for gravitational interaction, the pipeline processor generated by PGPG achieved the performance similar to that of hand-written code. In this paper we present a detailed description of PGPG version 1.0.Comment: 24 pages, 6 figures, accepted PASJ 2005 July 2

Monitoring and debugging using an SDK for NFV-powered telecom applications

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