Large-signal charge control modeling of photoreceivers for applications up to 40 Gb/s

A charge control model was used to simulate the sensitivity and responsivity in a range of photodetector configurations including heterojunction bipolar phototransistors (HPTs), PIN-HBT, and APDs. Our simulations enabled for the first time a direct comparison of the performance between these photodetectors to be made. Simulations have been performed at bit rates from 2 to 40 Gb/s using various combinations of device design parameters (layer thickness, source resistance, and dc base voltage). For a BER = 10(-9) at 40 Gb/s the best sensitivity of approximately -20 dBm was achieved using an optimized APD-HBT configuration, followed by sensitivities of approximately -14 dBm using optimized PIN-HBTs and HPTs. These results were found to agree well with published experimental data

Fundamental Blocks for a 0.18um Cyclic Analog-to-Digital Converter

The goal of this project was to design a fully differential Cyclic Analog-to-Digital Converter, and test the functionality of its major blocks. The converter is an integrated circuit designed for the CMOS 0.18 micron fabrication process. It is self-calibrating and performs 1 million samples per second. Design techniques used include switched capacitor networks, differential amplifier, replica biasing, and calibration in the off-chip digital domain. The project is sponsored by the New England Center for Analog and Mixed Signal Design (NECAMSID)

Monolithic large-signal transimpedance amplifier for use in multi-gigabit, short-range optoelectronic interconnect applications

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