Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

Adaptation of the IEEE 802.11 protocol for inter-satellite links in LEO satellite networks

Knowledge of the coefficient of thermal expansion (CTE) of a ceramic material is important in many application areas. Whilst the CTE can be measured, it would be useful to be able to predict the expansion behaviour of multiphase materials.. There are several models for the CTE, however, most require a knowledge of the elastic properties of the constituent phases and do not take account ofthe microstructural features of the material. If the CTE could be predicted on the basis of microstructural information, this would then lead to the ability to engineer the microstructure of multiphase ceramic materials to produce acceptable thermal expansion behaviour. To investigate this possibility, magnesia-magnesium aluminate sp~el (MMAS) composites, consisting of a magnesia matrix and magnesium aluminate s~ne'l (MAS) particles, were studied. Having determined a procedure to produce MAS fr alumina and magnesia, via solid state sintering, magnesia-rich compositions wit ~ various magnesia contents were prepared to make the MMAS composites. Further, the l\.1MAS composites prepared from different powders (i.e. from an alumina-magnesia mixture ahd from a magnesia-spinel powder) were compared. Com starch was added into the powder mixtures before sintering to make porous microstructures. Microstructural development and thermal expansion behaviour ofthe MMAS composites were investigated. Microstructures of the MAS and the MMAS composites as well as their porous bodies were quaritified from backscattered electron micrographs in terms of the connectivity of solids i.e. solid contiguity by means of linear intercept counting. Solid contiguity decreased with increasing pore content and varied with pore size, pore shape and pore distribution whereas the phase contiguity depended strongly on the chemical composition and was less influenced by porosity. ' The thermal expansion behaviour of the MAS and the MMAS composites between 100 and 1000 °C was determined experimentally. Variation in the CTE ofthe MAS relates to the degree of spinel formation while the thermal expansion of the MMAS composites depends strongly on phase content. However, the MMAS composites with similar phase compositions but made from different manufacturing processes showed differences in microstructural features and thermal expansion behaviour. Predictions of the CTE values for composites based on a simple rule-of-mixtures (ROM) using volume fraction were compared with the measured data. A conventional ROM accurately predicted the effective CTE of a range of dense alumina-silicon carbide particulate composites but was not very accurate for porous multiphase structures. It provided an upper bound prediction as all experimental values were lower. Hence, the conventional ROM was modified to take account of quantitative microstructural parameters obtained from solid contiguity. The modified ROM predicted lower values and gave a good agreement with the experimental data. Thus, it has been shown that quantitative microstructural information can be used to predict the CTE of multiphase ceramic materials with complex microstructures.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Wireless Network Communications Overview for Space Mission Operations

The mission of the On-Board Wireless Working Group (WWG) is to serve as a general CCSDS focus group for intra-vehicle wireless technologies. The WWG investigates and makes recommendations pursuant to standardization of applicable wireless network protocols, ensuring the interoperability of independently developed wireless communication assets. This document presents technical background information concerning uses and applicability of wireless networking technologies for space missions. Agency-relevant driving scenarios, for which wireless network communications will provide a significant return-on-investment benefiting the participating international agencies, are used to focus the scope of the enclosed technical information

Fault-tolerant satellite computing with modern semiconductors

Miniaturized satellites enable a variety space missions which were in the past infeasible, impractical or uneconomical with traditionally-designed heavier spacecraft. Especially CubeSats can be launched and manufactured rapidly at low cost from commercial components, even in academic environments. However, due to their low reliability and brief lifetime, they are usually not considered suitable for life- and safety-critical services, complex multi-phased solar-system-exploration missions, and missions with a longer duration. Commercial electronics are key to satellite miniaturization, but also responsible for their low reliability: Until 2019, there existed no reliable or fault-tolerant computer architectures suitable for very small satellites. To overcome this deficit, a novel on-board-computer architecture is described in this thesis.Robustness is assured without resorting to radiation hardening, but through software measures implemented within a robust-by-design multiprocessor-system-on-chip. This fault-tolerant architecture is component-wise simple and can dynamically adapt to changing performance requirements throughout a mission. It can support graceful aging by exploiting FPGA-reconfiguration and mixed-criticality.  Experimentally, we achieve 1.94W power consumption at 300Mhz with a Xilinx Kintex Ultrascale+ proof-of-concept, which is well within the powerbudget range of current 2U CubeSats. To our knowledge, this is the first COTS-based, reproducible on-board-computer architecture that can offer strong fault coverage even for small CubeSats.European Space AgencyComputer Systems, Imagery and Medi

Custom optimization algorithms for efficient hardware implementation

The focus is on real-time optimal decision making with application in advanced control systems. These computationally intensive schemes, which involve the repeated solution of (convex) optimization problems within a sampling interval, require more efficient computational methods than currently available for extending their application to highly dynamical systems and setups with resource-constrained embedded computing platforms. A range of techniques are proposed to exploit synergies between digital hardware, numerical analysis and algorithm design. These techniques build on top of parameterisable hardware code generation tools that generate VHDL code describing custom computing architectures for interior-point methods and a range of first-order constrained optimization methods. Since memory limitations are often important in embedded implementations we develop a custom storage scheme for KKT matrices arising in interior-point methods for control, which reduces memory requirements significantly and prevents I/O bandwidth limitations from affecting the performance in our implementations. To take advantage of the trend towards parallel computing architectures and to exploit the special characteristics of our custom architectures we propose several high-level parallel optimal control schemes that can reduce computation time. A novel optimization formulation was devised for reducing the computational effort in solving certain problems independent of the computing platform used. In order to be able to solve optimization problems in fixed-point arithmetic, which is significantly more resource-efficient than floating-point, tailored linear algebra algorithms were developed for solving the linear systems that form the computational bottleneck in many optimization methods. These methods come with guarantees for reliable operation. We also provide finite-precision error analysis for fixed-point implementations of first-order methods that can be used to minimize the use of resources while meeting accuracy specifications. The suggested techniques are demonstrated on several practical examples, including a hardware-in-the-loop setup for optimization-based control of a large airliner.Open Acces